Renesas SH7641 Manual do Utilizador

Revision Date: Sep. 14, 200532 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series SH7641 HD6417

Rev. 4.00 Sep. 14, 2005 Page x of l Abbreviations ADC Analog to digital converter ALU Arithmetic logic unit bpp bits per pixel bps bits per seco

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 50 of 982 REJ09B0023-0400 Addressing Mode Instruction Format Effective Address Calculation Method C

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 950 of 982 REJ09B0023-0400 TrcTrc Tr c Tr cTrrTpwTptCSD1tAD1tAD1tRWD1tRWD1tRW

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 951 of 982 REJ09B0023-0400 Trc Trc Trc Tmw TdeTrrTrrTpwTp TrctCSD1tAD1tA

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 952 of 982 REJ09B0023-0400 Tr Tc Tnop Trw1 TapTapTdeTd1TcTrtAD3tAD3CKIOA25 to

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 953 of 982 REJ09B0023-0400 Trc Trc Tr cTrrTpwTp(Hi-Z)*3tAD3tAD3tCSD2tCSD

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 954 of 982 REJ09B0023-0400 25.3.8 Peripheral Module Signal Timing Table 25.9

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 955 of 982 REJ09B0023-0400 tScyc tTXDSCKTxD (data transmission)RxD (data

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 956 of 982 REJ09B0023-0400 25.3.9 Multi Function Timer Pulse Unit Timing Tab

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 957 of 982 REJ09B0023-0400 25.3.10 POE Module Signal Timing Table 25.11

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 958 of 982 REJ09B0023-0400 25.3.11 I2C Module Signal Timing Table 25.12 I2C

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 959 of 982 REJ09B0023-0400 SCLVIHVILtSTAHtBUFP* S*tSFtSRtSCLtSDAHtSCLHtS

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 51 of 982 REJ09B0023-0400 Addressing Mode Instruction Format Effective Address Calculation Meth

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 960 of 982 REJ09B0023-0400 25.3.12 H-UDI Related Pin Timing Table 25.13 H-U

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 961 of 982 REJ09B0023-0400 tTRSTStTRSTHTRSTRESETP Figure 25.52 TRST In

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 962 of 982 REJ09B0023-0400 25.3.13 USB Module Signal Timing Table 25.14 USB

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 963 of 982 REJ09B0023-0400 25.3.14 USB Transceiver Timing Table 25.15

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 964 of 982 REJ09B0023-0400 25.3.15 AC Characteristics Measurement Conditions

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 965 of 982 REJ09B0023-0400 25.4 A/D Converter Characteristics Table 25.

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 966 of 982 REJ09B0023-0400

Appendix Rev. 4.00 Sep. 14, 2005 Page 967 of 982 REJ09B0023-0400 Appendix A. Pin States A.1 When Other Function is Selected Table A.1 Pin S

Appendix Rev. 4.00 Sep. 14, 2005 Page 968 of 982 REJ09B0023-0400 Reset State Power Down Mode Type Pin Name Power-On Manual Software Standby

Appendix Rev. 4.00 Sep. 14, 2005 Page 969 of 982 REJ09B0023-0400 Reset State Power Down Mode Type Pin Name Power-On Manual Software Sta

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 52 of 982 REJ09B0023-0400 X/Y Data Addressing: With DSP instructions, the X and Y data memory can be

Appendix Rev. 4.00 Sep. 14, 2005 Page 970 of 982 REJ09B0023-0400 [Legend] I: Input I+: Input with weak keeper I++: Input with pull-up MOS O: Out

Appendix Rev. 4.00 Sep. 14, 2005 Page 971 of 982 REJ09B0023-0400 A.2 When I/O Port is Selected Table A.2 Pin States in Reset State, Power D

Appendix Rev. 4.00 Sep. 14, 2005 Page 972 of 982 REJ09B0023-0400 B. Product Lineup Product Model Package (Code) SH7641 HD6417641BP100 (100 MHz v

Appendix Rev. 4.00 Sep. 14, 2005 Page 973 of 982 REJ09B0023-0400 C. Package Dimensions Package CodeJEDECJEITAP-LFBGA-1717-256––0.35 to 0.450.

Appendix Rev. 4.00 Sep. 14, 2005 Page 974 of 982 REJ09B0023-0400

Rev. 4.00 Sep. 14, 2005 Page 975 of 982 REJ09B0023-0400 Main Revisions and Additions in this Edition Item Page Revisions (See Manual for Deta

Rev. 4.00 Sep. 14, 2005 Page 976 of 982 REJ09B0023-0400 Item Page Revisions (See Manual for Details) Section 25 Electrical Characteristics Figure

Rev. 4.00 Sep. 14, 2005 Page 977 of 982 REJ09B0023-0400 Index Numerics 16-Bit/32-Bit displacement... 47 A A/D conversio

Rev. 4.00 Sep. 14, 2005 Page 978 of 982 REJ09B0023-0400 Direct Memory Access Controller... 405 Divider...

Rev. 4.00 Sep. 14, 2005 Page 979 of 982 REJ09B0023-0400 Multiply and accumulate high register ... 26 Multiply and accumulate low register..

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 53 of 982 REJ09B0023-0400 ALUAUR8[Ix] R4[Ax]R5[Ax]R9[Iy] R6[Ay]R7[Ay]+2 (INC)+0 (no update)+2 (I

Rev. 4.00 Sep. 14, 2005 Page 980 of 982 REJ09B0023-0400 ICDRS ... 487 ICDRT ...

Rev. 4.00 Sep. 14, 2005 Page 981 of 982 REJ09B0023-0400 USBEPDR0i ... 756 USBEPDR0o ...

Rev. 4.00 Sep. 14, 2005 Page 982 of 982 REJ09B0023-0400 X X/Y data addressing... 52 X/Y memory ...

Renesas 32-Bit RISC MicrocomputerHardware ManualSH7641Publication Date: Rev.1.00 Sep 19, 2003 Rev.4.00 S

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SH7641Hardware Manual

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 54 of 982 REJ09B0023-0400 The R8 register is the index register (Is) for the address pointer (As). Si

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 55 of 982 REJ09B0023-0400 MOV.L ModAddr,Rn; Rn=ModEnd, ModStart LDC Rn,MOD; ME=ModEnd,

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 56 of 982 REJ09B0023-0400 An example of modulo addressing is given below. MS = H'7000; ME=H&apos

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 57 of 982 REJ09B0023-0400 DSP Addressing Operations: DSP addressing operations in the pipeline e

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 58 of 982 REJ09B0023-0400 2.4.3 CPU Instruction Formats Table 2.13 shows the instruction formats, and

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 59 of 982 REJ09B0023-0400 Instruction Format Source Operand Destination Operand Sample Instruct

Rev. 4.00 Sep. 14, 2005 Page xi of l USB Universal serial bus WDT Watch dog timer

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 60 of 982 REJ09B0023-0400 Instruction Format Source Operand Destination Operand Sample Instruction d

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 61 of 982 REJ09B0023-0400 2.4.4 DSP Instruction Formats This LSI includes new instructions for d

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 62 of 982 REJ09B0023-0400 Double and Single Data Transfer Instructions: The format of double data tra

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 63 of 982 REJ09B0023-0400 Table 2.15 Single Data Transfer Instruction Formats Type Mnemonic 1

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 64 of 982 REJ09B0023-0400 Table 2.16 A-Field Parallel Data Transfer Instructions NOPXMOVX.W @Ax, DxM

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 65 of 982 REJ09B0023-0400 Table 2.17 B-Field ALU Operation Instructions and Multiply Instructio

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 66 of 982 REJ09B0023-0400 Table 2.17 B-Field ALU Operation Instructions and Multiply Instructions (2

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 67 of 982 REJ09B0023-0400 2.5 Instruction Set 2.5.1 CPU Instruction Set The SH-1/SH-2/SH-3 compa

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 68 of 982 REJ09B0023-0400 Type Kinds of Instruction Op Code Function Number of Instructions 21 MU

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 69 of 982 REJ09B0023-0400 Type Kinds of Instruction Op Code Function Number of Instructions B

Rev. 4.00 Sep. 14, 2005 Page xii of l

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 70 of 982 REJ09B0023-0400 The instruction code, operation, and number of execution states of the CPU

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 71 of 982 REJ09B0023-0400 Data Transfer Instructions Table 2.19 Data Transfer Instructions Ins

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 72 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States T Bit MOV.L Rm,

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 73 of 982 REJ09B0023-0400 Arithmetic Operation Instructions Table 2.20 Arithmetic Operation Ins

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 74 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States T Bit DMULU.L R

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 75 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States T Bit SUBV

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 76 of 982 REJ09B0023-0400 Shift Instructions Table 2.22 Shift Instructions Instruction Instruction

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 77 of 982 REJ09B0023-0400 Branch Instructions Table 2.23 Branch Instructions Instruction Inst

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 78 of 982 REJ09B0023-0400 System Control Instructions Table 2.24 System Control Instructions Instru

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 79 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States T Bit LDC.

Rev. 4.00 Sep. 14, 2005 Page xiii of l Contents Section 1 Overview...

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 80 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States T Bit STC R7_BA

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 81 of 982 REJ09B0023-0400 2.6 DSP Extended-Function Instructions 2.6.1 Introduction The newly a

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 82 of 982 REJ09B0023-0400 2.6.2 Added CPU System Control Instructions The new instructions in this c

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 83 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States T BitSTS.L

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 84 of 982 REJ09B0023-0400 2.6.3 Single and Double Data Transfer for DSP Data Instructions The new in

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 85 of 982 REJ09B0023-0400 Table 2.26 Double Data Transfer Instructions Instruction Instruction

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 86 of 982 REJ09B0023-0400 Table 2.27 Single Data Transfer Instructions Instruction Instruction Cod

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 87 of 982 REJ09B0023-0400 The correspondence between DSP data transfer operands and registers is

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 88 of 982 REJ09B0023-0400 2.6.4 DSP Operation Instruction Set DSP operation instructions are instruc

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 89 of 982 REJ09B0023-0400 Table 2.30 Correspondence between DSP Instruction Operands and Regist

Rev. 4.00 Sep. 14, 2005 Page xiv of l 3.1.5 Shift Operations...

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 90 of 982 REJ09B0023-0400 Table 2.31 DSP Operation Instructions Instruction Instruction Code Oper

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 91 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States DCDCF PSHA

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 92 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States DC PDMSB Sx,Dz

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 93 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States DC PNEG Sy

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 94 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States DC PDEC Sy,Dz

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 95 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States DC DCT PS

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 96 of 982 REJ09B0023-0400 Table 2.32 DC Bit Update Definitions CS [2:0] Condition Mode Description

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 97 of 982 REJ09B0023-0400 Conditional Operations and Data Transfer: Some instructions belonging

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 98 of 982 REJ09B0023-0400 Assignment of NOPX and NOPY Instruction Codes: When there is no data transf

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 99 of 982 REJ09B0023-0400 Section 3 DSP Operation 3.1 Data Operations of DSP Unit 3

Rev. 4.00 Sep. 14, 2005 Page xv of l 6.2 Register Descriptions...

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 100 of 982 REJ09B0023-0400 Table 3.1 Variation of ALU Fixed-Point Operations Mnemonic Fun

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 101 of 982 REJ09B0023-0400 IF12MOVXMOVXMOVXMOVX & PADDMOVX & PADDMOVX & PA

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 102 of 982 REJ09B0023-0400 Negative Value Mode: CS[2:0] = 001: The DC flag indicates the sa

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 103 of 982 REJ09B0023-0400 Signed Greater Than Mode: CS[2:0] = 100: The DC bit indicat

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 104 of 982 REJ09B0023-0400 3.1.2 ALU Integer Operations Figure 3.6 shows the ALU integer ar

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 105 of 982 REJ09B0023-0400 In ALU integer arithmetic operations, the lower word of the

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 106 of 982 REJ09B0023-0400 39 31 0Soruce 10DestinationALUDSRGT Z N VDC0Source 2Ignore

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 107 of 982 REJ09B0023-0400 5. Signed Greater Than Mode: CS[2:0] = 100 The DC bit is a

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 108 of 982 REJ09B0023-0400 Table 3.5 Variation of Fixed-Point Multiply Operation Mnemonic

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 109 of 982 REJ09B0023-0400 3.1.5 Shift Operations Shift operations can use either regi

Rev. 4.00 Sep. 14, 2005 Page xvi of l 9.1.1 TRAPA Exception Register (TRA) ...

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 110 of 982 REJ09B0023-0400 In this arithmetic shift operation, all bits of the source 1 and

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 111 of 982 REJ09B0023-0400 Overflow Protection: The S bit in SR is also effective for

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 112 of 982 REJ09B0023-0400 1. Carry or Borrow Mode: CS[2:0] = 000 The DC bit indicates the

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 113 of 982 REJ09B0023-0400 Every time a PDMSB operation is executed, the DC, N, Z, V,

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 114 of 982 REJ09B0023-0400 Table 3.8 Operation Definition of PDMSB Source Data Result for

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 115 of 982 REJ09B0023-0400 Table 3.9 Variation of PDMSB Operation Mnemonic Function

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 116 of 982 REJ09B0023-0400 0DestinationALUDSRClearedGT Z N VDCH'0000800039 31 0S

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 117 of 982 REJ09B0023-0400 3.1.8 Overflow Protection The S bit in SR is effective for

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 118 of 982 REJ09B0023-0400 3.1.9 Data Transfer Operation This LSI can execute a maximum of

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 119 of 982 REJ09B0023-0400 X pointer (R4, R5)0, +2, +R8XAB [15:1] YAB [15:1]XDB [15:0]

Rev. 4.00 Sep. 14, 2005 Page xvii of l 10.6.2 Timing to Clear an Interrupt Source ...

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 120 of 982 REJ09B0023-0400 Note: Data transfer by an LDS or STS instruction is possible si

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 121 of 982 REJ09B0023-0400 LAB [31:0]LDB [31:0]–4, 0, +4, +R8Pointer (R2, R3, R4, R5)A

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 122 of 982 REJ09B0023-0400 3.1.10 Local Data Move Instruction The DSP unit of this LSI pro

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 123 of 982 REJ09B0023-0400 3.1.11 Operand Conflict When an identical destination opera

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 124 of 982 REJ09B0023-0400 3.2 DSP Addressing 3.2.1 DSP Repeat Control This LSI prepares a

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 125 of 982 REJ09B0023-0400 #imm is 8 bits while RC is 12 bits. Therefore, to set more

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 126 of 982 REJ09B0023-0400 5. If a repeat loop has four or more instructions in it, any br

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 127 of 982 REJ09B0023-0400 In figure 3.18, exceptions generated by instructions marked

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 128 of 982 REJ09B0023-0400 Start(End):instr – 1instr0instr1instr2; A; B; C; A1. 1 repeated

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 129 of 982 REJ09B0023-0400 Based on this table, the actual repeat programming for vari

Rev. 4.00 Sep. 14, 2005 Page xviii of l 12.4.4 SDRAM Control Register (SDCR)...

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 130 of 982 REJ09B0023-0400 CASE 4: 4 or More Repeated Instructions LDRS RptStart;

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 131 of 982 REJ09B0023-0400 CASE 1: 1 Repeated Instruction REPEAT RptStart, RptStart,

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 132 of 982 REJ09B0023-0400 CASE 4: 4 or More Repeated Instructions REPEAT RptStart, RptEnd

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 133 of 982 REJ09B0023-0400 Table 3.18 Summary of DSP Data Transfer Instructions X a

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 134 of 982 REJ09B0023-0400 Three address operation types:1. Not update2. Add-index-regist

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 135 of 982 REJ09B0023-0400 ALUR8 [Is] R4 [As]R5 [As]R2 [As]R3 [As]–2/–4 (DEC)+2/+4 (IN

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 136 of 982 REJ09B0023-0400 MS and ME are set to specify the start and end addresses, and th

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 137 of 982 REJ09B0023-0400 An example is shown below. MS=H'7000; ME=H'7004;

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 138 of 982 REJ09B0023-0400 Addressing Instructions in Execution Stage: Address instructions

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 139 of 982 REJ09B0023-0400 /* The value to be added to the address register depends on

Rev. 4.00 Sep. 14, 2005 Page xix of l Section 14 U Memory...

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 140 of 982 REJ09B0023-0400 3115 10R4 [Ax]R5 [Ax]ABxXAB 16-bitX_MEMX R/WY_MEMY R/WYAB 16-bit

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 141 of 982 REJ09B0023-0400 Single-Data Transfer Instructions (MOVS.W and MOVS.L): This

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 142 of 982 REJ09B0023-0400 Control LAB=MAB; if ( Ms!=NLS && W/L is word access ) {

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 143 of 982 REJ09B0023-0400 Section 4 Clock Pulse Generator (CPG) This

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 144 of 982 REJ09B0023-0400 CKIOCKIO2PLL circuit 1(×1, 2, 3, 4)×1×1/2×1/3×1/4C

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 145 of 982 REJ09B0023-0400 The clock pulse generator blocks function as

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 146 of 982 REJ09B0023-0400 4.2 Input/Output Pins Table 4.1 lists the CPG pins

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 147 of 982 REJ09B0023-0400 Mode 2: The frequency of the signal received

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 148 of 982 REJ09B0023-0400 PLL frequency multiplier Selectable frequency rang

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 149 of 982 REJ09B0023-0400 4.4 Register Descriptions The CPG's cont

Rev. 4.00 Sep. 14, 2005 Page ii of l

Rev. 4.00 Sep. 14, 2005 Page xx of l 16.3.9 I2C Bus Shift Register (ICDRS)...

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 150 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 11, 10

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 151 of 982 REJ09B0023-0400 4.5 Changing the Frequency The frequency of

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 152 of 982 REJ09B0023-0400 4.6 Notes on Board Design Note on Using an Extern

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 153 of 982 REJ09B0023-0400 • A pair of Vss and Vcc for the input/output

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 154 of 982 REJ09B0023-0400

Section 5 Watchdog Timer (WDT) Rev. 4.00 Sep. 14, 2005 Page 155 of 982 REJ09B0023-0400 Section 5 Watchdog Timer (WDT) This LSI includes t

Section 5 Watchdog Timer (WDT) Rev. 4.00 Sep. 14, 2005 Page 156 of 982 REJ09B0023-0400 Figure 5.1 shows a block diagram of the WDT. WTCSRStandby

Section 5 Watchdog Timer (WDT) Rev. 4.00 Sep. 14, 2005 Page 157 of 982 REJ09B0023-0400 5.2.2 Watchdog Timer Control/Status Register (WTCSR

Section 5 Watchdog Timer (WDT) Rev. 4.00 Sep. 14, 2005 Page 158 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 4 WOVF 0 R/

Section 5 Watchdog Timer (WDT) Rev. 4.00 Sep. 14, 2005 Page 159 of 982 REJ09B0023-0400 5.2.3 Notes on Register Access The watchdog timer c

Rev. 4.00 Sep. 14, 2005 Page xxi of l 18.3.7 Timer General Register (TGR)...

Section 5 Watchdog Timer (WDT) Rev. 4.00 Sep. 14, 2005 Page 160 of 982 REJ09B0023-0400 5. When the WDT count overflows, the CPG starts supplyin

Section 5 Watchdog Timer (WDT) Rev. 4.00 Sep. 14, 2005 Page 161 of 982 REJ09B0023-0400 5.3.4 Using Interval Timer Mode When operating in i

Section 5 Watchdog Timer (WDT) Rev. 4.00 Sep. 14, 2005 Page 162 of 982 REJ09B0023-0400

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 163 of 982 REJ09B0023-0400 Section 6 Power-Down Modes In the low power-consumptio

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 164 of 982 REJ09B0023-0400 Table 6.1 States of Power-Down Modes State* Mode Transi

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 165 of 982 REJ09B0023-0400 • Manual-on reset 1. A low signal is input to the RESE

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 166 of 982 REJ09B0023-0400 6.2 Register Descriptions The following registers are used in

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 167 of 982 REJ09B0023-0400 6.2.2 Standby Control Register 2 (STBCR2) The standby c

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 168 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 2 MSTP5 0 R/W

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 169 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 6  0 R/W Re

Rev. 4.00 Sep. 14, 2005 Page xxii of l 18.7.13 Buffer Operation Setting in Complementary PWM Mode ... 636 18.7.14 R

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 170 of 982 REJ09B0023-0400 6.2.4 Standby Control Register 4 (STBCR4) STBCR4 is a readab

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 171 of 982 REJ09B0023-0400 6.3 Operation 6.3.1 Sleep Mode 1. Transition to Sleep M

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 172 of 982 REJ09B0023-0400 6.3.2 Standby Mode 1. Transition to Standby Mode The LSI swi

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 173 of 982 REJ09B0023-0400 2. Canceling Standby Mode Standby mode is canceled by i

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 174 of 982 REJ09B0023-0400 6.3.3 Module Standby Function 1. Transition to Module Standb

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 175 of 982 REJ09B0023-0400 1. Manual Reset CKIOSTATUS1. In manual reset, STATUS =

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 176 of 982 REJ09B0023-0400 B Standby mode is canceled by a manual reset CKIOSTATUS1.2.3

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 177 of 982 REJ09B0023-0400 B Sleep standby mode is canceled by a manual reset CKIO

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 178 of 982 REJ09B0023-0400

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 179 of 982 REJ09B0023-0400 Section 7 Cache 7.1 Features The cache specifications are listed

Rev. 4.00 Sep. 14, 2005 Page xxiii of l 19.3.12 Line Status Register (SCLSR) ...

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 180 of 982 REJ09B0023-0400 7.1.1 Cache Structure The cache mixes data and instructions and uses a 4

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 181 of 982 REJ09B0023-0400 Data Array: Holds a 16-byte instruction or data. Entries are regist

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 182 of 982 REJ09B0023-0400 7.2 Register Descriptions The cache has the following registers. • Cach

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 183 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 0 CE 0 R/W Cache Enable

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 184 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 31 to 17  All 0 R Reserved

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 185 of 982 REJ09B0023-0400 Table 7.4 Way to be Replaced when a Cache Miss Occurs in PREF Inst

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 186 of 982 REJ09B0023-0400 Table 7.7 LRU and Way Replacement (when W2LOCK=0 and W3LOCK=1) LRU (Bit

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 187 of 982 REJ09B0023-0400 01255V U Tag addressLW0 LW1 LW2 LW3Address array(ways 0 to 3)Data a

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 188 of 982 REJ09B0023-0400 7.3.2 Read Access Read Hit: In a read access, instructions and data are

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 189 of 982 REJ09B0023-0400 7.3.5 Write-Back Buffer When the U bit of the entry to be replaced

Rev. 4.00 Sep. 14, 2005 Page xxiv of l 20.4.4 EP1 Bulk-OUT Transfer (Dual FIFOs) ...

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 190 of 982 REJ09B0023-0400 7.4 Memory-Mapped Cache To allow software management of the cache, cache

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 191 of 982 REJ09B0023-0400 Data Array Read: The data specified by L (bits 3 and 2) in the addr

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 192 of 982 REJ09B0023-0400 7.4.3 Usage Examples Invalidating Specific Entries Specific cache entrie

Section 8 X/Y Memory Rev. 4.00 Sep. 14, 2005 Page 193 of 982 REJ09B0023-0400 Section 8 X/Y Memory This LSI has on-chip X-RAM and Y-RAM. I

Section 8 X/Y Memory Rev. 4.00 Sep. 14, 2005 Page 194 of 982 REJ09B0023-0400 8.2 X/Y Memory Access from CPU The X/Y memory can be accessed by t

Section 8 X/Y Memory Rev. 4.00 Sep. 14, 2005 Page 195 of 982 REJ09B0023-0400 8.4 X/Y Memory Access from DMAC The X/Y memory can be accesse

Section 8 X/Y Memory Rev. 4.00 Sep. 14, 2005 Page 196 of 982 REJ09B0023-0400

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 197 of 982 REJ09B0023-0400 Section 9 Exception Handling Exception handling is s

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 198 of 982 REJ09B0023-0400 9.1 Register Descriptions There are three registers for exc

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 199 of 982 REJ09B0023-0400 9.1.2 Exception Event Register (EXPEVT) EXPEVT is ass

Rev. 4.00 Sep. 14, 2005 Page xxv of l 21.3.6 Input Sampling and A/D Conversion Time ... 810

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 200 of 982 REJ09B0023-0400 9.2 Exception Handling Function 9.2.1 Exception Handling

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 201 of 982 REJ09B0023-0400 The above operations from 1 to 3 are executed in seque

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 202 of 982 REJ09B0023-0400 other than the CPU are not initialized, the contents of EXP

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 203 of 982 REJ09B0023-0400 If multiple general exceptions occur simultaneously in

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 204 of 982 REJ09B0023-0400 Table 9.1 Exception Event Vectors Exception Type Current I

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 205 of 982 REJ09B0023-0400 9.3 Individual Exception Operations This section descr

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 206 of 982 REJ09B0023-0400 Table 9.2 Type of Reset Internal state Type Condition to r

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 207 of 982 REJ09B0023-0400 Illegal general instruction exception: • Conditions 

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 208 of 982 REJ09B0023-0400 Unconditional trap: • Conditions TRAPA instruction execute

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 209 of 982 REJ09B0023-0400 DMA address error: • Conditions  Word data accessed

Rev. 4.00 Sep. 14, 2005 Page xxvi of l 23.4.2 Port D Data Register (PDDR)...

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 210 of 982 REJ09B0023-0400 9.4 Exception Processing While DSP Extension Function is V

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 211 of 982 REJ09B0023-0400 • Example 1: Repeat loop consisting of four instructi

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 212 of 982 REJ09B0023-0400 • Example 3: Repeat loop consisting of two instructions LD

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 213 of 982 REJ09B0023-0400 Table 9.4 SPC Value When a Re-Execution Type Exceptio

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 214 of 982 REJ09B0023-0400 An Exception Retained in Repeat Control Period: In the repe

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 215 of 982 REJ09B0023-0400 CPU Address Error in Repeat Control Period: If a CPU a

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 216 of 982 REJ09B0023-0400 9.5 Note on Initializing this LSI This LSI needs to be ini

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 217 of 982 REJ09B0023-0400 ;-----------------------------------------------------

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 218 of 982 REJ09B0023-0400 9.6 Usage Notes 1. An instruction assigned at a delay slot

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 219 of 982 REJ09B0023-0400 Section 10 Interrupt Controller (INTC) The

Rev. 4.00 Sep. 14, 2005 Page xxvii of l 25.3.12 H-UDI Related Pin Timing...

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 220 of 982 REJ09B0023-0400 Figure 10.1 shows a block diagram of the INTC. D

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 221 of 982 REJ09B0023-0400 10.2 Input/Output Pins Table 10.1 shows the

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 222 of 982 REJ09B0023-0400 • Interrupt mask register 6 (IMR6) • Interrupt

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 223 of 982 REJ09B0023-0400 10.3.1 Interrupt Priority Registers B to J (

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 224 of 982 REJ09B0023-0400 Table 10.2 Interrupt Sources and IPRB to IPRJ Re

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 225 of 982 REJ09B0023-0400 10.3.2 Interrupt Control Register 0 (ICR0) I

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 226 of 982 REJ09B0023-0400 10.3.3 Interrupt Control Register 1 (ICR1) ICR1 i

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 227 of 982 REJ09B0023-0400 10.3.4 Interrupt Control Register 3 (ICR3) I

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 228 of 982 REJ09B0023-0400 10.3.5 Interrupt Request Register 0 (IRR0) IRR0 i

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 229 of 982 REJ09B0023-0400 10.3.6 Interrupt Mask Registers 0 to 10 (IM

Rev. 4.00 Sep. 14, 2005 Page xxviii of l

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 230 of 982 REJ09B0023-0400 Table 10.3 Correspondence between Interrupt Sour

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 231 of 982 REJ09B0023-0400 10.3.7 Interrupt Mask Clear Registers 0 to

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 232 of 982 REJ09B0023-0400 Table 10.4 Correspondence between Interrupt Sour

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 233 of 982 REJ09B0023-0400 10.4 Interrupt Sources There are four types

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 234 of 982 REJ09B0023-0400 Edge input interrupt detection requires input of

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 235 of 982 REJ09B0023-0400 10.4.5 Interrupt Exception Handling and Prio

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 236 of 982 REJ09B0023-0400 Table 10.5 Interrupt Exception Handling Sources

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 237 of 982 REJ09B0023-0400 Interrupt Source Exception Code Interrup

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 238 of 982 REJ09B0023-0400 10.5 INTC Operation 10.5.1 Interrupt Sequence The

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 239 of 982 REJ09B0023-0400 I3 to I0: Interrupt mask bits in status reg

Rev. 4.00 Sep. 14, 2005 Page xxix of l Figures Section 1 Overview Figure 1.1 Block Diagram ...

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 240 of 982 REJ09B0023-0400 10.5.2 Multiple Interrupts When handling multiple

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 241 of 982 REJ09B0023-0400 Section 11 User Break Controller (UBC) The

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 242 of 982 REJ09B0023-0400 Figure 11.1 shows a block diagram of the UBC. BBR

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 243 of 982 REJ09B0023-0400 11.2 Register Descriptions The user break co

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 244 of 982 REJ09B0023-0400 11.2.2 Break Address Mask Register A (BAMRA) BAMR

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 245 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 246 of 982 REJ09B0023-0400 11.2.4 Break Address Register B (BARB) BARB is a

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 247 of 982 REJ09B0023-0400 11.2.5 Break Address Mask Register B (BAMRB)

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 248 of 982 REJ09B0023-0400 Table 11.2 Specifying Break Data Register Bus Se

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 249 of 982 REJ09B0023-0400 11.2.8 Break Bus Cycle Register B (BBRB) Bre

Rev. 4.00 Sep. 14, 2005 Page iii of l 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Techno

Rev. 4.00 Sep. 14, 2005 Page xxx of l Figure 3.14 Data Transfer Operation Flow...

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 250 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5 4 ID

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 251 of 982 REJ09B0023-0400 11.2.9 Break Control Register (BRCR) BRCR s

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 252 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 13 SC

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 253 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 6

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 254 of 982 REJ09B0023-0400 11.2.10 Execution Times Break Register (BETR) BE

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 255 of 982 REJ09B0023-0400 11.2.12 Branch Destination Register (BRDR)

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 256 of 982 REJ09B0023-0400 11.3 Operation 11.3.1 Flow of the User Break Ope

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 257 of 982 REJ09B0023-0400  If a logical address issued on the L bus

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 258 of 982 REJ09B0023-0400 4. When an instruction fetch cycle is set for ch

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 259 of 982 REJ09B0023-0400 word data in bits 31 to 16 in BDRB and BDMRB

Rev. 4.00 Sep. 14, 2005 Page xxxi of l Section 11 User Break Controller (UBC) Figure 11.1 Block Diagram of User Break Controller...

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 260 of 982 REJ09B0023-0400 11.3.5 Sequential Break 1. By setting the SEQ bi

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 261 of 982 REJ09B0023-0400 4. When data access (address + data) is spe

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 262 of 982 REJ09B0023-0400 11.3.8 Usage Examples Break Condition Specified f

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 263 of 982 REJ09B0023-0400 After an instruction with and address H&apos

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 264 of 982 REJ09B0023-0400 (Example 1-5) • Register specifications BARA = H

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 265 of 982 REJ09B0023-0400 Break Condition Specified for L Bus Data Acc

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 266 of 982 REJ09B0023-0400 Break Condition Specified for I Bus Data Access C

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 267 of 982 REJ09B0023-0400 4. When a user break and another exception

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 268 of 982 REJ09B0023-0400

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 269 of 982 REJ09B0023-0400 Section 12 Bus State Controller (BSC) The b

Rev. 4.00 Sep. 14, 2005 Page xxxii of l Figure 12.28 Single Write Timing (Bank Active, Different Row Addresses in the Same Bank) ...

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 270 of 982 REJ09B0023-0400  Supports low-frequency and power-down modes. 

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 271 of 982 REJ09B0023-0400 BSC functional block diagram is shown in figu

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 272 of 982 REJ09B0023-0400 12.2 Input/Output Pins Table 12.1 shows pin config

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 273 of 982 REJ09B0023-0400 Name I/O Function WE0 Output Indicates that

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 274 of 982 REJ09B0023-0400 12.3.2 Shadow Area Areas 0, 2 to 4, 5A, 5B, 6A, an

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 275 of 982 REJ09B0023-0400 12.3.3 Address Map The external address space

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 276 of 982 REJ09B0023-0400 Table 12.3 Address Space Map 2 (CMNCR.MAP = 1) Ph

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 277 of 982 REJ09B0023-0400 12.3.4 Area 0 Memory Type and Memory Bus Wid

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 278 of 982 REJ09B0023-0400 • Refresh timer control/status register (RTCSR) •

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 279 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1

Rev. 4.00 Sep. 14, 2005 Page xxxiii of l Figure 13.8 Example of DMA Transfer Timing in Single Address Mode... 436

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 280 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5 DMAI

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 281 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 0

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 282 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 27 26

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 283 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 2

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 284 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 14 13

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 285 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 286 of 982 REJ09B0023-0400 12.4.3 CSn Space Wait Control Register (CSnWCR) (

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 287 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 10

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 288 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1 0 HW

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 289 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1

Rev. 4.00 Sep. 14, 2005 Page xxxiv of l Figure 16.9 Slave Transmit Mode Operation Timing (1) ...

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 290 of 982 REJ09B0023-0400 • CS4WCR Bit Bit Name Initial Value R/W Descripti

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 291 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 12

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 292 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5 to 2

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 293 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 12

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 294 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5 to 2

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 295 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 20

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 296 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 12 11 S

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 297 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 298 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 10 9 8

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 299 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1

Rev. 4.00 Sep. 14, 2005 Page xxxv of l Figure 18.20 Example of PWM Mode Setting Procedure ...

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 300 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 10 9 8

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 301 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 302 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 17 16 B

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 303 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 6

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 304 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 17 16 B

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 305 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 10

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 306 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1 0 HW1

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 307 of 982 REJ09B0023-0400 • CS3WCR Bit Bit Name Initial Value R/W Desc

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 308 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 9  0

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 309 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 2

Rev. 4.00 Sep. 14, 2005 Page xxxvi of l Figure 18.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) ...

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 310 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 19 MPX

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 311 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 15

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 312 of 982 REJ09B0023-0400 Burst ROM (Clock Synchronous): • CS0WCR Bit Bit N

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 313 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 10

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 314 of 982 REJ09B0023-0400 12.4.4 SDRAM Control Register (SDCR) SDCR specifi

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 315 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 13

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 316 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 9 PDOWN

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 317 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 2

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 318 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 6  0

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 319 of 982 REJ09B0023-0400 12.4.6 Refresh Timer Counter (RTCNT) RTCNT is

Rev. 4.00 Sep. 14, 2005 Page xxxvii of l Figure 18.90 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous PWM Mode...

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 320 of 982 REJ09B0023-0400 12.4.8 Reset Wait Counter (RWTCNT) RWTCNT is a 7-

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 321 of 982 REJ09B0023-0400 12.5 Operating Description 12.5.1 Endian/Acc

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 322 of 982 REJ09B0023-0400 Table 12.6 16-Bit External Device Access and Data

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 323 of 982 REJ09B0023-0400 Table 12.7 8-Bit External Device Access and

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 324 of 982 REJ09B0023-0400 12.5.2 Normal Space Interface Basic Timing: For ac

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 325 of 982 REJ09B0023-0400 It is necessary to output the data that has b

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 326 of 982 REJ09B0023-0400 CKIOA25 to A0RD/WRD15 to D0DACKnCSnT1 T2 T1 T

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 327 of 982 REJ09B0023-0400 ••••••••••••••••••••A16A0CSOEI/O7I/O0WE••••••

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 328 of 982 REJ09B0023-0400 A16A0CSOEI/O7I/O0WE••••••••••••••••A17A1CSnRDD15D8

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 329 of 982 REJ09B0023-0400 12.5.3 Access Wait Control Wait cycle insert

Rev. 4.00 Sep. 14, 2005 Page xxxviii of l Figure 18.117 Output-Level Detection Operation ...

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 330 of 982 REJ09B0023-0400 When the WM bit in CSnWCR is cleared to 0, the ext

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 331 of 982 REJ09B0023-0400 12.5.4 CSn Assert Period Expansion The numbe

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 332 of 982 REJ09B0023-0400 12.5.5 MPX-I/O Interface Access timing for the MPX

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 333 of 982 REJ09B0023-0400 T1CKIOA25 to A16CSnRD/WRRDD7 to D0 orD15 to D

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 334 of 982 REJ09B0023-0400 T1CKIOA25 to A16CS5BRD/WRRDD7 to D0 orD15 to D0 WE

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 335 of 982 REJ09B0023-0400 12.5.6 SDRAM Interface SDRAM Direct Connectio

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 336 of 982 REJ09B0023-0400 Figures 12.15 to 12.17 show examples of the connec

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 337 of 982 REJ09B0023-0400 A14A1CKECKIOCSnRASUCASURASLCASLRD/WRD15D0DQML

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 338 of 982 REJ09B0023-0400 A14A1CKECKIOCSnRASUCASURASLCASLRD/WRD15D16DQMLUDQM

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 339 of 982 REJ09B0023-0400 Address Multiplexing: An address multiplexing

Rev. 4.00 Sep. 14, 2005 Page xxxix of l Figure 20.16 EP2 PKTE Operation ...

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 340 of 982 REJ09B0023-0400 Table 12.8 Relationship between BSZ1, 0, A2/3ROW1

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 341 of 982 REJ09B0023-0400 Table 12.8 Relationship between BSZ1, 0, A2/

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 342 of 982 REJ09B0023-0400 Table 12.9 Relationship between BSZ1, 0, A2/3ROW1

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 343 of 982 REJ09B0023-0400 Table 12.9 Relationship between BSZ1, 0, A2/

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 344 of 982 REJ09B0023-0400 Table 12.10 Relationship between BSZ1, 0, A2/3ROW

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 345 of 982 REJ09B0023-0400 Table 12.11 Relationship between BSZ1, 0, A2

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 346 of 982 REJ09B0023-0400 Table 12.11 Relationship between BSZ1, 0, A2/3ROW

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 347 of 982 REJ09B0023-0400 Table 12.12 Relationship between BSZ1, 0, A2

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 348 of 982 REJ09B0023-0400 Table 12.12 Relationship between BSZ1, 0, A2/3ROW

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 349 of 982 REJ09B0023-0400 Table 12.13 Relationship between BSZ1, 0, A2

Rev. 4.00 Sep. 14, 2005 Page iv of l General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC p

Rev. 4.00 Sep. 14, 2005 Page xl of l Section 25 Electrical Characteristics Figure 25.1 Power-On Sequence ...

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 350 of 982 REJ09B0023-0400 Table 12.13 Relationship between BSZ1, 0, A2/3ROW

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 351 of 982 REJ09B0023-0400 Burst Read: A burst read occurs in the follow

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 352 of 982 REJ09B0023-0400 number of cycles from the Tc1 cycle where the READ

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 353 of 982 REJ09B0023-0400 Tc4(Tap)Tr Tc2 Tc3Tc1Td4TdeTd2 Td3Td1TrwTwCKI

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 354 of 982 REJ09B0023-0400 Single Read: A read access ends in one cycle when

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 355 of 982 REJ09B0023-0400 Burst Write: A burst write occurs in the foll

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 356 of 982 REJ09B0023-0400 Tc4 TapTr Tc2 Tc3Tc1 Trwl CKIOA25 to A0CSnRD/WRRA

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 357 of 982 REJ09B0023-0400 Single Write: A write access ends in one cycl

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 358 of 982 REJ09B0023-0400 Bank Active: The synchronous DRAM bank function is

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 359 of 982 REJ09B0023-0400 When bank active mode is set, if only accesse

Rev. 4.00 Sep. 14, 2005 Page xli of l Figure 25.27 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, TRWL = 1 Cycle) ...

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 360 of 982 REJ09B0023-0400 Tc4Tc2 Tc3Tc1TnopTd4TdeTd2 Td3Td1CKIOA25 to A0CSnR

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 361 of 982 REJ09B0023-0400 Tc4TpwTp Tc2 Tc3Tc1Td4Td2 Td3Td1TdeTrCKIOA25

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 362 of 982 REJ09B0023-0400 Tr Tc1CKIOA25 to A0CSnRD/WRRASL, RASUDQMxxD31 to D

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 363 of 982 REJ09B0023-0400 TnopTc1CKIOA25 to A0CSnRD/WRRASL, RASUDQMxxD3

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 364 of 982 REJ09B0023-0400 TpwTpTc1TrCKIOA25 to A0CSnRD/WRRASL, RASUDQMxxD31

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 365 of 982 REJ09B0023-0400 1. Auto-refreshing Refreshing is performed at

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 366 of 982 REJ09B0023-0400 TpwTpTrr Trc TrcTrcHi-zCKIOA25 to A0CSnRD/WRRASL,

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 367 of 982 REJ09B0023-0400 Self-refresh timing is shown in figure 12.30.

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 368 of 982 REJ09B0023-0400 Relationship between Refresh Requests and Bus Cycl

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 369 of 982 REJ09B0023-0400 Tc1TrTd1 TdeTapTr Tc1TnopTrwlTap(High)CKIOCKE

Rev. 4.00 Sep. 14, 2005 Page xlii of l Figure 25.48 MTU Clock Input Timing ...

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 370 of 982 REJ09B0023-0400 TnopPower-downTr Tc1Td1 Tde TapPower-downCKIOCKEA2

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 371 of 982 REJ09B0023-0400 Power-On Sequence: In order to use synchronou

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 372 of 982 REJ09B0023-0400 • Setting for Area 3 Burst read/single write (bu

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 373 of 982 REJ09B0023-0400 TpwTpTrrTrc TrcTmwHi-ZTnopTrcTrrTrcREF REF MR

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 374 of 982 REJ09B0023-0400 Table 12.16 Output Addresses when EMRS Command Is

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 375 of 982 REJ09B0023-0400 • Deep power-down mode The low-power SDRAM s

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 376 of 982 REJ09B0023-0400 12.5.7 Burst ROM (Clock Asynchronous) Interface T

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 377 of 982 REJ09B0023-0400 CKIOA25 to A0RDD15 to D0DACKn*Note: * The wav

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 378 of 982 REJ09B0023-0400 CKIOA25 to A0CSnWEnRD/WRRDRDD31 to D0D31 to D0RD/W

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 379 of 982 REJ09B0023-0400 T1T2HighCKIOA25 to A0CSnWEnRD/WRRDRDD31 to D0

Rev. 4.00 Sep. 14, 2005 Page xliii of l Tables Section 1 Overview Table 1.1 Features...

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 380 of 982 REJ09B0023-0400 T2ThTh T1 TwHighCKIOA25 to A0CSnWEnRD/WRRDRDD31 to

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 381 of 982 REJ09B0023-0400 A15A0CSOEWEI/O15I/O0UBLB. . . . . .. . .A17A2

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 382 of 982 REJ09B0023-0400 12.5.9 Burst MPX-I/O Interface Figure 12.42 shows

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 383 of 982 REJ09B0023-0400 Tm1 Tmd1wTmd1ADNote: * The waveform for DACK

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 384 of 982 REJ09B0023-0400 Tm1 Tmd1w Tmd1wTmd1ADNote: * The waveform for DACK

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 385 of 982 REJ09B0023-0400 Tm1 Tmd1w Tmd1 Tmd2Tmd3Tmd4AD0D1D2D3Note: * T

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 386 of 982 REJ09B0023-0400 Note: * The waveform for DACKn is when active low

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 387 of 982 REJ09B0023-0400 The burst ROM interface performs burst operat

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 388 of 982 REJ09B0023-0400 6. Data output from an external device caused by

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 389 of 982 REJ09B0023-0400 Tables 12.18 to 12.22 lists the minimum numbe

Rev. 4.00 Sep. 14, 2005 Page xliv of l Table 2.31 DSP Operation Instructions ...

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 390 of 982 REJ09B0023-0400 Table 12.19 Minimum Number of Idle Cycles between

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 391 of 982 REJ09B0023-0400 Table 12.20 Minimum Number of Idle Cycles du

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 392 of 982 REJ09B0023-0400 (2) Transfer from the normal space interface to t

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 393 of 982 REJ09B0023-0400 Table 12.21 Minimum Number of Idle Cycles be

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 394 of 982 REJ09B0023-0400 BSC Register Setting CPU Access DMAC Access CS

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 395 of 982 REJ09B0023-0400 BSC Register Setting CPU Access DMAC Acce

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 396 of 982 REJ09B0023-0400 Table 12.22 Minimum Number of Idle Cycles between

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 397 of 982 REJ09B0023-0400 BSC Register Setting*2 CMNCR.DMAIW Setting C

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 398 of 982 REJ09B0023-0400 (2) Transfer from the SDRAM interface to the exte

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 399 of 982 REJ09B0023-0400 12.5.12 Bus Arbitration The bus arbitration o

Rev. 4.00 Sep. 14, 2005 Page xlv of l Table 7.8 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 1)... 186 Section 8 X/Y Memory

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 400 of 982 REJ09B0023-0400 The sequence for reclaiming the bus mastership fro

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 401 of 982 REJ09B0023-0400 12.5.13 Others Reset: The bus state controlle

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 402 of 982 REJ09B0023-0400 If the CPU initiates read access for the cache, th

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 403 of 982 REJ09B0023-0400 DMA source and destination addresses exist in

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 404 of 982 REJ09B0023-0400

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 405 of 982 REJ09B0023-0400 Section 13 Direct Memory Access

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 406 of 982 REJ09B0023-0400 • Transfer request acknowledge and tr

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 407 of 982 REJ09B0023-0400 13.2 Input/Output Pins The extern

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 408 of 982 REJ09B0023-0400 13.3 Register Descriptions Register co

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 409 of 982 REJ09B0023-0400 13.3.1 DMA Source Address Regist

Rev. 4.00 Sep. 14, 2005 Page xlvi of l Table 12.10 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (3)...

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 410 of 982 REJ09B0023-0400 13.3.4 DMA Channel Control Registers

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 411 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W De

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 412 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Descrip

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 413 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W De

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 414 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Descrip

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 415 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W De

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 416 of 982 REJ09B0023-0400 13.3.5 DMA Operation Register (DMAOR)

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 417 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W D

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 418 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Descrip

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 419 of 982 REJ09B0023-0400 If (PR1 and PR0) = (B'10) is

Rev. 4.00 Sep. 14, 2005 Page xlvii of l Section 14 U Memory Table 14.1 U Memory Specifications ...

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 420 of 982 REJ09B0023-0400 Table 13.2 Combination of the Round-R

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 421 of 982 REJ09B0023-0400 13.3.6 DMA Extension Resource Se

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 422 of 982 REJ09B0023-0400 • DMARS1 Bit Bit Name Initial Value R

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 423 of 982 REJ09B0023-0400 Transfer requests from the variou

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 424 of 982 REJ09B0023-0400 13.4 Operation When there is a DMA tra

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 425 of 982 REJ09B0023-0400 Figure 13.2 is a flowchart of thi

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 426 of 982 REJ09B0023-0400 13.4.2 DMA Transfer Requests DMA tran

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 427 of 982 REJ09B0023-0400 Table 13.5 Selecting External Re

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 428 of 982 REJ09B0023-0400 On-Chip Peripheral Module Request: In

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 429 of 982 REJ09B0023-0400 CHCR DMARS RS[3:0] MID RID D

Rev. 4.00 Sep. 14, 2005 Page xlviii of l Table 18.27 Output Level Select Function ...

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 430 of 982 REJ09B0023-0400 These are selected by the PR1 and the

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 431 of 982 REJ09B0023-0400 Figure 13.4 shows how the priorit

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 432 of 982 REJ09B0023-0400 13.4.4 DMA Transfer Types DMA transfe

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 433 of 982 REJ09B0023-0400 Address Modes: 1. Dual Address M

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 434 of 982 REJ09B0023-0400 Figure 13.6 shows an example of DMA tr

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 435 of 982 REJ09B0023-0400 DMACThis LSIDACKDREQExternal addr

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 436 of 982 REJ09B0023-0400 Figure 13.8 shows example of DMA trans

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 437 of 982 REJ09B0023-0400 Figure 13.9 shows an example of D

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 438 of 982 REJ09B0023-0400 DREQCPU CPUBus cycle CPU DMAC DMAC CPU

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 439 of 982 REJ09B0023-0400 Table 13.9 Relationship of Reque

Rev. 4.00 Sep. 14, 2005 Page xlix of l Table 21.4 A/D Conversion Time (Multi Mode and Scan Mode) ... 811 Ta

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 440 of 982 REJ09B0023-0400 Bus Mode and Channel Priority Order: W

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 441 of 982 REJ09B0023-0400 CKIO1st acceptance 2nd acceptance

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 442 of 982 REJ09B0023-0400 CKIOCPU CPU DMACCKIOCPU CPU DMACDMAC1s

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 443 of 982 REJ09B0023-0400 To execute a longword access to a

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 444 of 982 REJ09B0023-0400 13.4.6 Completion of DMA Transfer The

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 445 of 982 REJ09B0023-0400 • When an address error occurs d

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 446 of 982 REJ09B0023-0400 6. Note the followings when the DMA t

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 447 of 982 REJ09B0023-0400 • Idle cycles between read-read

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 448 of 982 REJ09B0023-0400 CPUDMAC writeNon-sensitive period1st a

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 449 of 982 REJ09B0023-0400 CPUCPUDMAC writeDMAC writeNon-sen

Rev. 4.00 Sep. 14, 2005 Page v of l Important Notice on the Quality Assurance for this LSI Although the wafer process and assembly process of this

Rev. 4.00 Sep. 14, 2005 Page l of l Appendix Table A.1 Pin States in Reset State, Power Down Mode, and Bus-Released States When Other Function

Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 450 of 982 REJ09B0023-0400

Section 14 U Memory Rev. 4.00 Sep. 14, 2005 Page 451 of 982 REJ09B0023-0400 Section 14 U Memory This LSI has on-chip U memory. It can be

Section 14 U Memory Rev. 4.00 Sep. 14, 2005 Page 452 of 982 REJ09B0023-0400 14.2 U Memory Access from CPU The U memory can be accessed by the C

Section 14 U Memory Rev. 4.00 Sep. 14, 2005 Page 453 of 982 REJ09B0023-0400 14.5 Usage Note When accessing the U memory by the CPU or the D

Section 14 U Memory Rev. 4.00 Sep. 14, 2005 Page 454 of 982 REJ09B0023-0400

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 455 of 982 REJ09B0023-0400 Section 15 User Debugging Interface (

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 456 of 982 REJ09B0023-0400 15.2 Input/Output Pins Table 15.1 shows the

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 457 of 982 REJ09B0023-0400 15.3 Register Descriptions The H-UDI ha

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 458 of 982 REJ09B0023-0400 Table 15.2 H-UDI Commands Bits 15 to 8 TI7

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 459 of 982 REJ09B0023-0400 Table 15.3 This LSI Pins and Boundary

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 1 of 982 REJ09B0023-0400 Section 1 Overview This LSI is a single-chip RISC microprocessor

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 460 of 982 REJ09B0023-0400 Bit Pin Name I/O Bit Pin Name I/O 424 D

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 461 of 982 REJ09B0023-0400 Bit Pin Name I/O Bit Pin Name I/O 36

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 462 of 982 REJ09B0023-0400 Bit Pin Name I/O Bit Pin Name I/O 296 CT

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 463 of 982 REJ09B0023-0400 Bit Pin Name I/O Bit Pin Name I/O 23

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 464 of 982 REJ09B0023-0400 Bit Pin Name I/O Bit Pin Name I/O 168 D

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 465 of 982 REJ09B0023-0400 Bit Pin Name I/O Bit Pin Name I/O

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 466 of 982 REJ09B0023-0400 Bit Pin Name I/O Bit Pin Name I/O 40 D20/

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 467 of 982 REJ09B0023-0400 15.3.4 ID Register (SDID) The ID regis

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 468 of 982 REJ09B0023-0400 15.4 Operation 15.4.1 TAP Controller Figure

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 469 of 982 REJ09B0023-0400 15.4.2 Reset Configuration Table 15.4

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 2 of 828 REJ09B0023-0400 Items Specification DSP • Mixture of 16-bit and 32-bit instructions •

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 470 of 982 REJ09B0023-0400 TDO(when the H-UDI command is set)TCKTDO(whe

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 471 of 982 REJ09B0023-0400 15.5 Boundary Scan A command can be set

Section 15 User Debugging Interface (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 472 of 982 REJ09B0023-0400 EXTEST: This instruction is provided to test

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 473 of 982 REJ09B0023-0400 Section 16 I2C Bus Interface 2 (IIC2) The I

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 474 of 982 REJ09B0023-0400 SCLICCR1Transfer clockgenerationcircuitAddresscomp

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 475 of 982 REJ09B0023-0400 VccQ* VccQ*SCL in SCL outSCLSDA in SDA outS

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 476 of 982 REJ09B0023-0400 16.3 Register Descriptions The I2C bus interface 2

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 477 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 478 of 982 REJ09B0023-0400 Table 16.2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 479 of 982 REJ09B0023-0400 16.3.2 I2C Bus Control Register 2 (ICCR2) ICC

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 3 of 982 REJ09B0023-0400 Items Specification Cache memory • 16-kbyte cache, mixed instruct

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 480 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 4 SDAO

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 481 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5,

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 482 of 982 REJ09B0023-0400 16.3.4 I2C Bus Interrupt Enable Register (ICIER) I

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 483 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 3

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 484 of 982 REJ09B0023-0400 16.3.5 I2C Bus Status Register (ICSR) ICSR is an 8

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 485 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 4

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 486 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1 AAS

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 487 of 982 REJ09B0023-0400 16.3.7 I2C Bus Transmit Data Register (ICDRT)

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 488 of 982 REJ09B0023-0400 16.4 Operation The I2C bus interface can communica

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 489 of 982 REJ09B0023-0400 [Legend] S: Start condition. The master dev

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 4 of 828 REJ09B0023-0400 Items Specification Bus state controller (BSC) • Physical address spac

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 490 of 982 REJ09B0023-0400 TDRESCL(Master output)SDA(Master output)SDA(Slave

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 491 of 982 REJ09B0023-0400 16.4.3 Master Receive Operation In master rec

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 492 of 982 REJ09B0023-0400 TDRETENDICDRSICDRR[1] Clear TDRE after clearing

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 493 of 982 REJ09B0023-0400 RDRFRCVDICDRSICDRRData n-1Data nData nData n-

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 494 of 982 REJ09B0023-0400 5. Clear TDRE. TDRETENDICDRSICDRR1A2134567899ATRS

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 495 of 982 REJ09B0023-0400 TDREData nTENDICDRSICDRR19 23456789TRSICDRTAS

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 496 of 982 REJ09B0023-0400 16.4.5 Slave Receive Operation In slave receive mo

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 497 of 982 REJ09B0023-0400 ICDRSICDRR12345678 99AARDRFSCL(Master output)

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 498 of 982 REJ09B0023-0400 Transmit Operation: In transmit mode, transmit dat

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 499 of 982 REJ09B0023-0400 Receive Operation: In receive mode, data is l

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 5 of 982 REJ09B0023-0400 Items Specification Advanced user debugger (AUD) • Six output pin

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 500 of 982 REJ09B0023-0400 12 781 7812SCLMSTTRSRDRFICDRSICDRRSDA(Input)Bit 0B

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 501 of 982 REJ09B0023-0400 16.4.7 Noise Filter The logic levels at the S

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 502 of 982 REJ09B0023-0400 16.4.8 Example of Use Flowcharts in respective mod

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 503 of 982 REJ09B0023-0400 NoYesRDRF=1 ?NoYesRDRF=1 ?Last receive- 1?Mat

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 504 of 982 REJ09B0023-0400 TDRE=1 ?YesYesNoSlave transmit modeClear AAS in IC

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 505 of 982 REJ09B0023-0400 NoYesRDRF=1 ?NoYesRDRF=1 ?Last receive - 1?Sl

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 506 of 982 REJ09B0023-0400 16.5 Interrupt Request There are six interrupt req

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 507 of 982 REJ09B0023-0400 16.6 Bit Synchronous Circuit In master mode,

Section 16 I2C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 508 of 982 REJ09B0023-0400 16.7 Usage Note Start (retransmission) and stop co

Section 17 Compare Match Timer (CMT) Rev. 4.00 Sep. 14, 2005 Page 509 of 982 REJ09B0023-0400 Section 17 Compare Match Timer (CMT) This LS

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 6 of 828 REJ09B0023-0400 Items Specification Compare match timer (CMT) • 16-bit counter × 2 cha

Section 17 Compare Match Timer (CMT) Rev. 4.00 Sep. 14, 2005 Page 510 of 982 REJ09B0023-0400 17.2 Register Descriptions The CMT has the followin

Section 17 Compare Match Timer (CMT) Rev. 4.00 Sep. 14, 2005 Page 511 of 982 REJ09B0023-0400 17.2.2 Compare Match Timer Control/Status Reg

Section 17 Compare Match Timer (CMT) Rev. 4.00 Sep. 14, 2005 Page 512 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 1 0 CKS1

Section 17 Compare Match Timer (CMT) Rev. 4.00 Sep. 14, 2005 Page 513 of 982 REJ09B0023-0400 17.3 Operation 17.3.1 Interval Count Operation

Section 17 Compare Match Timer (CMT) Rev. 4.00 Sep. 14, 2005 Page 514 of 982 REJ09B0023-0400 17.4 Compare Matches 17.4.1 Timing of Compare Matc

Section 17 Compare Match Timer (CMT) Rev. 4.00 Sep. 14, 2005 Page 515 of 982 REJ09B0023-0400 17.4.3 Timing of Compare Match Flag Clearing

Section 17 Compare Match Timer (CMT) Rev. 4.00 Sep. 14, 2005 Page 516 of 982 REJ09B0023-0400

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 517 of 982 REJ09B0023-0400 Section 18 Multi-Function Timer

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 518 of 982 REJ09B0023-0400 Table 18.1 MTU Functions Item Channel

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 519 of 982 REJ09B0023-0400 Item Channel 0 Channel 1 Channe

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 7 of 982 REJ09B0023-0400 1.2 Block Diagram The block diagram of this LSI is shown in figure

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 520 of 982 REJ09B0023-0400 Internal data busA/D converter conversi

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 521 of 982 REJ09B0023-0400 18.2 Input/Output Pins Table 18.2

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 522 of 982 REJ09B0023-0400 18.3 Register Descriptions The MTU has

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 523 of 982 REJ09B0023-0400 • Timer I/O control register L_3

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 524 of 982 REJ09B0023-0400 18.3.1 Timer Control Register (TCR) Th

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 525 of 982 REJ09B0023-0400 Table 18.3 CCLR0 to CCLR2 (Channe

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 526 of 982 REJ09B0023-0400 Table 18.5 TPSC0 to TPSC2 (Channel 0)

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 527 of 982 REJ09B0023-0400 Table 18.7 TPSC0 to TPSC2 (Channe

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 528 of 982 REJ09B0023-0400 18.3.2 Timer Mode Register (TMDR) The

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 529 of 982 REJ09B0023-0400 Table 18.9 MD0 to MD3 Bit 3 MD3 B

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 8 of 828 REJ09B0023-0400 1.3 Pin Assignments The pin assignments of this LSI is shown in figure

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 530 of 982 REJ09B0023-0400 18.3.3 Timer I/O Control Register (TIO

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 531 of 982 REJ09B0023-0400 • TIORL_0, TIORL_3, TIORL_4 Bit B

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 532 of 982 REJ09B0023-0400 Table 18.10 TIORH_0 (Channel 0) D

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 533 of 982 REJ09B0023-0400 Table 18.11 TIORL_0 (Channel 0)

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 534 of 982 REJ09B0023-0400 Table 18.12 TIOR_1 (Channel 1) De

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 535 of 982 REJ09B0023-0400 Table 18.13 TIOR_2 (Channel 2)

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 536 of 982 REJ09B0023-0400 Table 18.14 TIORH_3 (Channel 3) D

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 537 of 982 REJ09B0023-0400 Table 18.15 TIORL_3 (Channel 3)

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 538 of 982 REJ09B0023-0400 Table 18.16 TIORH_4 (Channel 4) D

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 539 of 982 REJ09B0023-0400 Table 18.17 TIORL_4 (Channel 4)

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 9 of 982 REJ09B0023-0400 1.4 Pin functions Table 1.2 summarizes the pin functions. Table 1.

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 540 of 982 REJ09B0023-0400 Table 18.18 TIORH_0 (Channel 0) D

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 541 of 982 REJ09B0023-0400 Table 18.19 TIORL_0 (Channel 0)

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 542 of 982 REJ09B0023-0400 Table 18.20 TIOR_1 (Channel 1) De

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 543 of 982 REJ09B0023-0400 Table 18.21 TIOR_2 (Channel 2)

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 544 of 982 REJ09B0023-0400 Table 18.22 TIORH_3 (Channel 3) D

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 545 of 982 REJ09B0023-0400 Table 18.23 TIORL_3 (Channel 3)

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 546 of 982 REJ09B0023-0400 Table 18.24 TIORH_4 (Channel 4) D

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 547 of 982 REJ09B0023-0400 Table 18.25 TIORL_4 (Channel 4)

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 548 of 982 REJ09B0023-0400 18.3.4 Timer Interrupt Enable Register

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 549 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Des

Rev. 4.00 Sep. 14, 2005 Page vi of l Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 10 of 828 REJ09B0023-0400 No. (BGA256) Pin Name Description J1 DPLS/PTB[8] USB D+ input from

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 550 of 982 REJ09B0023-0400 18.3.5 Timer Status Register (TSR) The

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 551 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Des

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 552 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Descript

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 553 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Des

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 554 of 982 REJ09B0023-0400 18.3.8 Timer Start Register (TSTR) TST

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 555 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Des

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 556 of 982 REJ09B0023-0400 18.3.10 Timer Output Master Enable Reg

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 557 of 982 REJ09B0023-0400 18.3.11 Timer Output Control Regi

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 558 of 982 REJ09B0023-0400 Table 18.27 Output Level Select Functi

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 559 of 982 REJ09B0023-0400 18.3.12 Timer Gate Control Registe

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 11 of 982 REJ09B0023-0400 No. (BGA256) Pin Name Description W1 VccQ Power supply for I/O

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 560 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Descript

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 561 of 982 REJ09B0023-0400 18.3.13 Timer Subcounter (TCNTS) T

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 562 of 982 REJ09B0023-0400 18.3.17 Bus Master Interface The timer

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 563 of 982 REJ09B0023-0400 Example of Count Operation Setting

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 564 of 982 REJ09B0023-0400 TCNT valueH'FFFFH'0000CST bit

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 565 of 982 REJ09B0023-0400 Example of Setting Procedure for W

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 566 of 982 REJ09B0023-0400 Figure 18.8 shows an example of toggle

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 567 of 982 REJ09B0023-0400 Example of Input Capture Operation

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 568 of 982 REJ09B0023-0400 TCNT valueH'0180H'0000TIOCATG

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 569 of 982 REJ09B0023-0400 Example of Synchronous Operation S

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 12 of 828 REJ09B0023-0400 No. (BGA256) Pin Name Description W9 TIOC3C/PTE[5] Timer input outp

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 570 of 982 REJ09B0023-0400 Example of Synchronous Operation: Figur

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 571 of 982 REJ09B0023-0400 18.4.3 Buffer Operation Buffer ope

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 572 of 982 REJ09B0023-0400 • When TGR is an input capture registe

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 573 of 982 REJ09B0023-0400 Examples of Buffer Operation: • W

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 574 of 982 REJ09B0023-0400 TCNT valueH'09FBH'0000TGRCTim

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 575 of 982 REJ09B0023-0400 Example of Cascaded Operation Sett

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 576 of 982 REJ09B0023-0400 18.4.5 PWM Modes In PWM mode, PWM wavef

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 577 of 982 REJ09B0023-0400 The correspondence between PWM out

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 578 of 982 REJ09B0023-0400 Example of PWM Mode Setting Procedure:

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 579 of 982 REJ09B0023-0400 Figure 18.22 shows an example of P

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 13 of 982 REJ09B0023-0400 No. (BGA256) Pin Name Description Y18 VssQ Ground for I/O circ

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 580 of 982 REJ09B0023-0400 Figure 18.23 shows examples of PWM wave

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 581 of 982 REJ09B0023-0400 18.4.6 Phase Counting Mode In phas

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 582 of 982 REJ09B0023-0400 Example of Phase Counting Mode Setting

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 583 of 982 REJ09B0023-0400 Table 18.33 Up/Down-Count Conditi

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 584 of 982 REJ09B0023-0400 Table 18.34 Up/Down-Count Conditions i

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 585 of 982 REJ09B0023-0400 Table 18.35 Up/Down-Count Conditi

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 586 of 982 REJ09B0023-0400 Table 18.36 Up/Down-Count Conditions i

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 587 of 982 REJ09B0023-0400 TCNT_1TCNT_0Channel 1TGRA_1(speed

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 588 of 982 REJ09B0023-0400 18.4.7 Reset-Synchronized PWM Mode In

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 589 of 982 REJ09B0023-0400 Procedure for Selecting the Reset-

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 14 of 828 REJ09B0023-0400 No. (BGA256) Pin Name Description N20 RESETP Power−on Reset request

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 590 of 982 REJ09B0023-0400 Reset-Synchronized PWM Mode Operation:

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 591 of 982 REJ09B0023-0400 18.4.8 Complementary PWM Mode In

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 592 of 982 REJ09B0023-0400 Table 18.40 Register Settings for Comp

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 593 of 982 REJ09B0023-0400 TGRC_3TDDRTCNT_3TGRD_3 TGRD_4TGRC_

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 594 of 982 REJ09B0023-0400 Example of Complementary PWM Mode Setti

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 595 of 982 REJ09B0023-0400 Outline of Complementary PWM Mode

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 596 of 982 REJ09B0023-0400 Counter valueTGRA_3TCDRTDDRH'0000T

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 597 of 982 REJ09B0023-0400 with the counter. In this interval

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 598 of 982 REJ09B0023-0400 Initialization: In complementary PWM mo

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 599 of 982 REJ09B0023-0400 Dead Time Setting: In complementar

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 15 of 982 REJ09B0023-0400 No. (BGA256) Pin Name Description F19 DACK0/PTC[11] DMA reques

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 600 of 982 REJ09B0023-0400 Counter valueTGRC_3updateTGRA_3updateTG

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 601 of 982 REJ09B0023-0400 Data update timing: counter crest

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 602 of 982 REJ09B0023-0400 Initial Output in Complementary PWM Mod

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 603 of 982 REJ09B0023-0400 Timer output control register sett

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 604 of 982 REJ09B0023-0400 Complementary PWM Mode PWM Output Gener

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 605 of 982 REJ09B0023-0400 T2 periodT1 periodT1 periodabca&ap

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 606 of 982 REJ09B0023-0400 T2 periodT1 periodT1 periodTGRA_3TCDRTD

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 607 of 982 REJ09B0023-0400 abca' b'dT1 period T2 pe

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 608 of 982 REJ09B0023-0400 Complementary PWM Mode 0% and 100% Duty

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 609 of 982 REJ09B0023-0400 T2 periodT1 period T1 periodTGRA_3

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 16 of 828 REJ09B0023-0400 No. (BGA256) Pin Name Description A14 WE0/DQMLL D7 to D0 Select sig

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 610 of 982 REJ09B0023-0400 TGRA_3TCDRTDDRH'0000Positive phase

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 611 of 982 REJ09B0023-0400 Toggle Output Synchronized with PW

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 612 of 982 REJ09B0023-0400 Counter Clearing by another Channel: In

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 613 of 982 REJ09B0023-0400 Example of AC Synchronous Motor (B

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 614 of 982 REJ09B0023-0400 External input TIOC0A pinTIOC0B pinTIOC

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 615 of 982 REJ09B0023-0400 TGCR UF bitVF bitWF bitTIOC3B pinT

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 616 of 982 REJ09B0023-0400 Some registers in channels 3 and 4 conc

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 617 of 982 REJ09B0023-0400 Table 18.42 MTU Interrupts Chann

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 618 of 982 REJ09B0023-0400 Overflow Interrupt: An interrupt is req

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 619 of 982 REJ09B0023-0400 18.6 Operation Timing 18.6.1 Input

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 17 of 982 REJ09B0023-0400 No. (BGA256) Pin Name Description C6 A1 Address bus A4 A0/PTA[

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 620 of 982 REJ09B0023-0400 PφExternal clockTCNT input clockTCNTFal

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 621 of 982 REJ09B0023-0400 PφTCNT inputclockTCNTNN+1TGRCompar

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 622 of 982 REJ09B0023-0400 Timing for Counter Clearing by Compare

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 623 of 982 REJ09B0023-0400 Buffer Operation Timing: Figures 1

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 624 of 982 REJ09B0023-0400 18.6.2 Interrupt Signal Timing TGF Flag

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 625 of 982 REJ09B0023-0400 TCFV Flag/TCFU Flag Setting Timing

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 626 of 982 REJ09B0023-0400 Status Flag Clearing Timing: After a st

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 627 of 982 REJ09B0023-0400 18.7 Usage Notes 18.7.1 Module St

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 628 of 982 REJ09B0023-0400 18.7.3 Caution on Period Setting When

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 629 of 982 REJ09B0023-0400 18.7.5 Conflict between TCNT Writ

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 18 of 828 REJ09B0023-0400 Table 1.3 lists the pin functions. Table 1.3 Pin Functions Classifica

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 630 of 982 REJ09B0023-0400 18.7.6 Conflict between TGR Write and C

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 631 of 982 REJ09B0023-0400 Comparematch buffersignalComparema

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 632 of 982 REJ09B0023-0400 18.7.8 Conflict between TGR Read and In

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 633 of 982 REJ09B0023-0400 18.7.9 Conflict between TGR Write

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 634 of 982 REJ09B0023-0400 18.7.10 Conflict between Buffer Regist

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 635 of 982 REJ09B0023-0400 T1 T2H'FFFE H'FFFF N N +

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 636 of 982 REJ09B0023-0400 18.7.12 Counter Value during Complemen

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 637 of 982 REJ09B0023-0400 buffer register for TGRA_3. At the

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 638 of 982 REJ09B0023-0400 18.7.15 Overflow Flags in Reset Sync P

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 639 of 982 REJ09B0023-0400 Counter clearsignalTCNTTCNT inputc

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 19 of 982 REJ09B0023-0400 Classification Symbol I/O Name Function CKIO O System clock S

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 640 of 982 REJ09B0023-0400 18.7.18 Cautions on Transition from No

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 641 of 982 REJ09B0023-0400 18.8 MTU Output Pin Initializatio

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 642 of 982 REJ09B0023-0400 18.8.3 Operation in Case of Re-Setting

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 643 of 982 REJ09B0023-0400 18.8.4 Overview of Initialization

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 644 of 982 REJ09B0023-0400 (1) Operation when Error Occurs during

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 645 of 982 REJ09B0023-0400 (2) Operation when Error Occurs d

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 646 of 982 REJ09B0023-0400 (3) Operation when Error Occurs during

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 647 of 982 REJ09B0023-0400 (4) Operation when Error Occurs d

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 648 of 982 REJ09B0023-0400 (5) Operation when Error Occurs during

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 649 of 982 REJ09B0023-0400 (6) Operation when Error Occurs d

Rev. 4.00 Sep. 14, 2005 Page vii of l

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 20 of 828 REJ09B0023-0400 Classification Symbol I/O Name Function Bus control RD/WR O Read/wr

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 650 of 982 REJ09B0023-0400 (7) Operation when Error Occurs during

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 651 of 982 REJ09B0023-0400 (8) Operation when Error Occurs d

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 652 of 982 REJ09B0023-0400 (9) Operation when Error Occurs during

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 653 of 982 REJ09B0023-0400 (10) Operation when Error Occurs

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 654 of 982 REJ09B0023-0400 (11) Operation when Error Occurs durin

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 655 of 982 REJ09B0023-0400 (12) Operation when Error Occurs

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 656 of 982 REJ09B0023-0400 (13) Operation when Error Occurs durin

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 657 of 982 REJ09B0023-0400 (14) Operation when Error Occurs

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 658 of 982 REJ09B0023-0400 (15) Operation when Error Occurs durin

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 659 of 982 REJ09B0023-0400 (16) Operation when Error Occurs

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 21 of 982 REJ09B0023-0400 Classification Symbol I/O Name Function DREQ0, DREQ1 I DMA-trans

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 660 of 982 REJ09B0023-0400 (17) Operation when Error Occurs durin

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 661 of 982 REJ09B0023-0400 (18) Operation when Error Occurs

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 662 of 982 REJ09B0023-0400 (19) Operation when Error Occurs durin

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 663 of 982 REJ09B0023-0400 (20) Operation when Error Occurs

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 664 of 982 REJ09B0023-0400 (21) Operation when Error Occurs durin

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 665 of 982 REJ09B0023-0400 (22) Operation when Error Occurs

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 666 of 982 REJ09B0023-0400 (23) Operation when Error Occurs durin

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 667 of 982 REJ09B0023-0400 (24) Operation when Error Occurs

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 668 of 982 REJ09B0023-0400 (25) Operation when Error Occurs durin

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 669 of 982 REJ09B0023-0400 (26) Operation when Error Occurs

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 22 of 828 REJ09B0023-0400 Classification Symbol I/O Name Function TCLKA TCLKB TCLKC TCLKD I Cl

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 670 of 982 REJ09B0023-0400 (27) Operation when Error Occurs durin

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 671 of 982 REJ09B0023-0400 (28) Operation when Error Occurs

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 672 of 982 REJ09B0023-0400 (29) Operation when Error Occurs durin

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 673 of 982 REJ09B0023-0400 18.9 Port Output Enable (POE) The

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 674 of 982 REJ09B0023-0400 The POE has input-level detection circu

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 675 of 982 REJ09B0023-0400 18.9.2 Pin Configuration Table 18.

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 676 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Descript

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 677 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Des

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 678 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Descript

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 679 of 982 REJ09B0023-0400 Output Level Control/Status Regist

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 23 of 982 REJ09B0023-0400 Classification Symbol I/O Name Function XVDATA I Data input I

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 680 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Descript

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 681 of 982 REJ09B0023-0400 18.9.4 Operation Input Level Detec

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 682 of 982 REJ09B0023-0400 2. Low-Level Detection Figure 18.116 sh

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 683 of 982 REJ09B0023-0400 Release from High-Impedance State:

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 684 of 982 REJ09B0023-0400

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 685 of 982 REJ09B0023-0400 Section 19 Serial Comm

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 686 of 982 REJ09B0023-0400 • Internal or external trans

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 687 of 982 REJ09B0023-0400 Module data busSCFRDR(16

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 688 of 982 REJ09B0023-0400 19.2 Pin Configuration The SC

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 689 of 982 REJ09B0023-0400 19.3 Register Descriptio

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 24 of 828 REJ09B0023-0400 Classification Symbol I/O Name Function PTA14 to PTA0 I/O General pur

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 690 of 982 REJ09B0023-0400 19.3.1 Receive Shift Register

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 691 of 982 REJ09B0023-0400 19.3.4 Transmit FIFO Da

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 692 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 693 of 982 REJ09B0023-0400 Bit Bit Name Initial val

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 694 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 695 of 982 REJ09B0023-0400 19.3.6 Serial Control R

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 696 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 697 of 982 REJ09B0023-0400 Bit Bit Name Initial val

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 698 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 699 of 982 REJ09B0023-0400 19.3.7 Serial Status Re

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 25 of 982 REJ09B0023-0400 Section 2 CPU 2.1 Registers This LSI has the same registers as the S

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 700 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 701 of 982 REJ09B0023-0400 Bit Bit Name Initial val

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 702 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 703 of 982 REJ09B0023-0400 Bit Bit Name Initial val

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 704 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 705 of 982 REJ09B0023-0400 Bit Bit Name Initial val

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 706 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 707 of 982 REJ09B0023-0400 19.3.8 Bit Rate Registe

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 708 of 982 REJ09B0023-0400 Table 19.3 lists examples of

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 709 of 982 REJ09B0023-0400 Pφ (MHz) 10 12 12.28

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 26 of 982 REJ09B0023-0400 The system registers are accessed by the LDS/STS instructions (the PC is so

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 710 of 982 REJ09B0023-0400 Pφ (MHz) 24.576 28.7 30

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 711 of 982 REJ09B0023-0400 Table 19.4 Bit Rates an

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 712 of 982 REJ09B0023-0400 Table 19.5 indicates the maxi

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 713 of 982 REJ09B0023-0400 Table 19.6 Maximum Bit

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 714 of 982 REJ09B0023-0400 19.3.9 FIFO Control Register

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 715 of 982 REJ09B0023-0400 Bit Bit Name Initial val

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 716 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 717 of 982 REJ09B0023-0400 19.3.10 FIFO Data Count

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 718 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 719 of 982 REJ09B0023-0400 Bit Bit Name Initial val

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 27 of 982 REJ09B0023-0400 31R0_BANK1*1, *2R1_BANK1*2R2_BANK1*2R3_BANK1*2R4_BANK1*2R5_BANK1*2R6_B

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 720 of 982 REJ09B0023-0400 19.3.12 Line Status Register

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 721 of 982 REJ09B0023-0400 19.4 Operation 19.4.1 Ov

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 722 of 982 REJ09B0023-0400 Table 19.8 SCSMR Settings an

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 723 of 982 REJ09B0023-0400 19.4.2 Operation in Asy

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 724 of 982 REJ09B0023-0400 Transmit/Receive Formats: Tab

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 725 of 982 REJ09B0023-0400 Transmitting and Receivi

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 726 of 982 REJ09B0023-0400 Figure 19.3 shows a sample fl

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 727 of 982 REJ09B0023-0400 • Transmitting Serial D

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 728 of 982 REJ09B0023-0400 In serial transmission, the S

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 729 of 982 REJ09B0023-0400 Figure 19.5 shows an exa

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 28 of 982 REJ09B0023-0400 39A0GA1G32 31A0A1M0M1X0X1Y0Y1DSRMSMEMOD0(c) DSP mode register configuration

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 730 of 982 REJ09B0023-0400 • Receiving Serial Data (Asy

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 731 of 982 REJ09B0023-0400 Error handlingReceive er

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 732 of 982 REJ09B0023-0400 In serial reception, the SCIF

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 733 of 982 REJ09B0023-0400 10 D0 D1 D7 0/1 1 0 D0 D

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 734 of 982 REJ09B0023-0400 Figure 19.11 shows the genera

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 735 of 982 REJ09B0023-0400 Figure 19.12 shows a sam

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 736 of 982 REJ09B0023-0400 • Transmitting Serial Data (

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 737 of 982 REJ09B0023-0400 In serial transmission,

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 738 of 982 REJ09B0023-0400 • Receiving Serial Data (Syn

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 739 of 982 REJ09B0023-0400 Error handlingClear ORER

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 29 of 982 REJ09B0023-0400 2.1.1 General Registers There are sixteen 32-bit general registers (Rn

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 740 of 982 REJ09B0023-0400 In serial reception, the SCIF

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 741 of 982 REJ09B0023-0400 • Transmitting and Rece

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 742 of 982 REJ09B0023-0400 19.5 SCIF Interrupts and DMA

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 743 of 982 REJ09B0023-0400 Table 19.11 SCIF Interr

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 744 of 982 REJ09B0023-0400 The number of receive data by

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 745 of 982 REJ09B0023-0400 0 1 2 3 4 5 6 7 8 9 10 1

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 746 of 982 REJ09B0023-0400 6. When Using the DMAC  Us

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 747 of 982 REJ09B0023-0400 Section 20 USB Function Module 20.1 Features • In

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 748 of 982 REJ09B0023-0400 • Power mode: Self-powered, bus-powered 20.1.1 Block Di

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 749 of 982 REJ09B0023-0400 In on-chip transceiver bypass mode (the XVEROFF bit

Rev. 4.00 Sep. 14, 2005 Page viii of l Preface The SH7641 RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas Technology origi

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 30 of 982 REJ09B0023-0400 On the other hand, registers R2 to R9 are also used for DSP data address ca

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 750 of 982 REJ09B0023-0400 20.3.1 USB Interrupt Flag Register 0 (USBIFR0) Together

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 751 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 2 EP0oTS

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 752 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 2 EP3TR 0 R

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 753 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1 CFGV 0

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 754 of 982 REJ09B0023-0400 20.3.5 USB Interrupt Select Register 1 (USBISR1) USBISR1

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 755 of 982 REJ09B0023-0400 20.3.7 USB Interrupt Enable Register 1 (USBIER1) US

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 756 of 982 REJ09B0023-0400 20.3.9 USBEP0i Data Register (USBEPDR0i) USBEPDR0i is an

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 757 of 982 REJ09B0023-0400 20.3.11 USBEP0s Data Register (USBEPDR0s) USBEPDR0s

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 758 of 982 REJ09B0023-0400 20.3.13 USBEP2 Data Register (USBEPDR2) USBEPDR2 is a 12

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 759 of 982 REJ09B0023-0400 20.3.16 USBEP1 Receive Data Size Register (USBEPSZ1)

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 31 of 982 REJ09B0023-0400 Ay1: .REG (R7) Iy: .REG (R9) As0: .REG (R4) ; This is optional, if an

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 760 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 2 EP0sRDFN 0

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 761 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 4 EP2DE

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 762 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 0 EP0iCLR 0 W

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 763 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 0 EP1DMA

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 764 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 2 EP2STL 0 R/

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 765 of 982 REJ09B0023-0400 20.3.23 USB Bus Power Control Register (USBCTRL) Th

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 766 of 982 REJ09B0023-0400 20.4 Operation 20.4.1 Cable Connection Cable disconnected

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 767 of 982 REJ09B0023-0400 Also, in applications that require connection detect

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 768 of 982 REJ09B0023-0400 20.4.3 Control Transfer Control transfer consists of thre

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 769 of 982 REJ09B0023-0400 Setup Stage: USB functionApplicationSETUP token rece

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 32 of 982 REJ09B0023-0400 and end addresses of a loop (the contents of the RS and RE registers are sl

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 770 of 982 REJ09B0023-0400 Data Stage (Control-IN): The application first analyzes c

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 771 of 982 REJ09B0023-0400 Data Stage (Control-OUT): The application first anal

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 772 of 982 REJ09B0023-0400 Status Stage (Control-IN): The control-IN status stage st

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 773 of 982 REJ09B0023-0400 Status Stage (Control-OUT): The control-OUT status s

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 774 of 982 REJ09B0023-0400 20.4.4 EP1 Bulk-OUT Transfer (Dual FIFOs) EP1 has two 64

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 775 of 982 REJ09B0023-0400 USB functionApplicationOUT token receptionData recep

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 776 of 982 REJ09B0023-0400 20.4.5 EP2 Bulk-IN Transfer (Dual FIFOs) EP2 has two 64-

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 777 of 982 REJ09B0023-0400 USB functionApplicationIN token receptionData transm

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 778 of 982 REJ09B0023-0400 20.4.6 EP3 Interrupt-IN Transfer USB functionApplication

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 779 of 982 REJ09B0023-0400 20.5 Processing of USB Standard Commands and Class/

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 33 of 982 REJ09B0023-0400 310 1 RC 0-0DSPDMY DMX M Q I3 I2 I1 I0RF1 RF0STRB BL28 27 16 15 13 12

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 780 of 982 REJ09B0023-0400 20.6 Stall Operations This section describes stall operat

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 781 of 982 REJ09B0023-0400 (1) Transition from normal operation to stall (1-1

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 782 of 982 REJ09B0023-0400 20.6.2 Automatic Stall by USB Function Module When a sta

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 783 of 982 REJ09B0023-0400 (1) Transition from normal operation to stall (1-1

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 784 of 982 REJ09B0023-0400 20.7 DMA Transfer This module allows DMAC transfer for en

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 785 of 982 REJ09B0023-0400 20.7.2 DMA Transfer for Endpoint 2 When the transmi

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 786 of 982 REJ09B0023-0400 20.8 Example of USB External Circuitry USB Transceiver:

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 787 of 982 REJ09B0023-0400 USB moduleGeneral output port, etc.IC that allows vo

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 788 of 982 REJ09B0023-0400 This LSIUSB moduleGeneral output port, etc.IC that allows

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 789 of 982 REJ09B0023-0400 20.9 USB Bus Power Control Method 20.9.1 USB Bus P

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 34 of 982 REJ09B0023-0400 SSR31 0Saved status register (SSR)SPC31 0Saved program counter (SPC)GBR31 0

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 790 of 982 REJ09B0023-0400 This LSIIRQ1IRQ1_SUSPENDUSBCTRL/SUSPENDUSBIFR2/SUSPSUSBIF

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 791 of 982 REJ09B0023-0400 Normal routine USIHP interrupt routinePower On Reset

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 792 of 982 REJ09B0023-0400 Normal routineIRQ1 interrupt routineNormal stateClear IRR

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 793 of 982 REJ09B0023-0400 Normal routineIRQ0 interrupt routineIRQ1interrupt ro

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 794 of 982 REJ09B0023-0400 20.10 Notes on Usage 20.10.1 Receiving Setup Data Note t

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 795 of 982 REJ09B0023-0400 20.10.4 Assigning Interrupt Source for EP0 Interrup

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 796 of 982 REJ09B0023-0400 TR interrupt routineTR interrupt routineCPUUSBClear TR fl

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 797 of 982 REJ09B0023-0400 Section 21 A/D Converter This LSI includes a 10-bit succ

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 798 of 982 REJ09B0023-0400 21.1.1 Block Diagram Figure 21.1 shows a block diagram of the A

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 799 of 982 REJ09B0023-0400 21.1.2 Input Pins Table 21.1 summarizes the A/D converter&

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 35 of 982 REJ09B0023-0400 2.1.3 System Registers This LSI has four system registers, MACL, MACH,

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 800 of 982 REJ09B0023-0400 21.1.3 Register Configuration The A/D converter's register

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 801 of 982 REJ09B0023-0400 Table 21.2 Analog Input Channels and A/D Data Registers A

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 802 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 14 ADIE 0 R/W A/

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 803 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 10 to 8  All

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 804 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1 0 CH1 CH0 0 0 R/W

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 805 of 982 REJ09B0023-0400 21.3 Operation The A/D converter operates by successive ap

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 806 of 982 REJ09B0023-0400 Channel 0 (AN0)operatingADIEADSTADFChannel 1 (AN1)operatingChan

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 807 of 982 REJ09B0023-0400 Typical operations when three channels in A/D0 (AN0 to AN2

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 808 of 982 REJ09B0023-0400 21.3.3 Scan Mode Scan mode is useful for monitoring analog inpu

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 809 of 982 REJ09B0023-0400 ADSTADFChannel 0 (AN0)operatingChannel 1 (AN1)operatingCha

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 36 of 982 REJ09B0023-0400 When data is read into the upper 16 bits of a register (bits 31 to 16), the

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 810 of 982 REJ09B0023-0400 21.3.5 A/D Converter Activation by MTU The A/D converter can b

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 811 of 982 REJ09B0023-0400 PφWritesignalADF ADCSR write cycleInput samplingtimingtD :

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 812 of 982 REJ09B0023-0400 21.4 Interrupt and DMAC Transfer Request The A/D converter gen

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 813 of 982 REJ09B0023-0400 21.5 Definitions of A/D Conversion Accuracy The A/D conve

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 814 of 982 REJ09B0023-0400 0FS111110101100011010001000Analog inputvoltage(3) Quantization

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 815 of 982 REJ09B0023-0400 21.6 Usage Notes When using the A/D converter, note the fo

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 816 of 982 REJ09B0023-0400 21.6.4 Influences on Absolute Precision Adding capacitance res

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 817 of 982 REJ09B0023-0400 0.01 µF10 µFAVCCAN0 to AN7AVSSThis LSI*11.100 Ω0.1 µFNote:

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 818 of 982 REJ09B0023-0400

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 819 of 982 REJ09B0023-0400 Section 22 Pin Function Controller (PFC)

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 37 of 982 REJ09B0023-0400 Table 2.2 Destination Register in DSP Instructions Guard Bits Re

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 820 of 982 REJ09B0023-0400 Port Port Function (Related Module) Other Fun

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 821 of 982 REJ09B0023-0400 Port Port Function (Related Module) Othe

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 822 of 982 REJ09B0023-0400 Port Port Function (Related Module) Other Fun

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 823 of 982 REJ09B0023-0400 Port Port Function (Related Module) Othe

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 824 of 982 REJ09B0023-0400 22.1.1 Port A Control Register (PACR) PACR is

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 825 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 826 of 982 REJ09B0023-0400 22.1.2 Port B Control Register (PBCR) PBCR is

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 827 of 982 REJ09B0023-0400 22.1.3 Port C Control Register (PCCR) PCC

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 828 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 7 6

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 829 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 38 of 982 REJ09B0023-0400 Table 2.3 Source Register in DSP Operations Guard Bits Register Bits

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 830 of 982 REJ09B0023-0400 22.1.5 Port E Control Register (PECR) PECR is

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 831 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 832 of 982 REJ09B0023-0400 22.1.6 Port E I/O Register (PEIOR) PEIOR is a

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 833 of 982 REJ09B0023-0400 22.1.7 Port E MTU R/W Enable Register (PE

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 834 of 982 REJ09B0023-0400 22.1.8 Port F Control Register (PFCR) PFCR is

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 835 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 836 of 982 REJ09B0023-0400 22.1.9 Port G Control Register (PGCR) PGCR is

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 837 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 838 of 982 REJ09B0023-0400 22.1.10 Port H Control Register (PHCR) PHCR is

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 839 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 39 of 982 REJ09B0023-0400 313239A0A0GA1GA1M0M1X0X1Y0Y101234567DCCS [2:0]VNZGT8310(a) DSP Data R

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 840 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 13 1

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 841 of 982 REJ09B0023-0400 22.2 I/O Buffer Internal Block Diagram 22

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 842 of 982 REJ09B0023-0400 SDA input dataSCL input dataSDA output dataSCL

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 843 of 982 REJ09B0023-0400 Section 23 I/O Ports This LSI has nine 16-bit ports (ports A

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 844 of 982 REJ09B0023-0400 23.1.2 Port A Data Register (PADR) PADR is a 15-bit readable/writa

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 845 of 982 REJ09B0023-0400 Table 23.1 Port A Data Register (PADR) Read/Write Operations

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 846 of 982 REJ09B0023-0400 23.2.2 Port B Data Register (PBDR) PBDR is a 9-bit readable/writab

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 847 of 982 REJ09B0023-0400 23.3 Port C Port C is a 16-bit input/output port with the pin

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 848 of 982 REJ09B0023-0400 23.3.2 Port C Data Register (PCDR) PCDR is a 16-bit readable/writa

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 849 of 982 REJ09B0023-0400 Table 23.3 Port C Data Register (PCDR) Read/Write Operations

Rev. 4.00 Sep. 14, 2005 Page ix of l Rules: Register name: The following notation is used for cases when the same or a similar function, e.g. ser

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 40 of 982 REJ09B0023-0400 The DSP unit has one control register, the DSP status register (DSR). DSR h

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 850 of 982 REJ09B0023-0400 23.4.1 Register Description Port D has the following register. • P

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 851 of 982 REJ09B0023-0400 Table 23.4 Port D Data Register (PDDR) Read/Write Operations

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 852 of 982 REJ09B0023-0400 23.5.1 Register Description Port E has the following register. • P

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 853 of 982 REJ09B0023-0400 Table 23.5 Port E Data Register (PEDR) Read/Write Operations

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 854 of 982 REJ09B0023-0400 23.6.1 Register Description Port F has the following register. • P

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 855 of 982 REJ09B0023-0400 Table 23.6 Port F Data Register (PFDR) Read/Write Operations

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 856 of 982 REJ09B0023-0400 23.7 Port G Port G comprises a 6-bit input/output port and an 8-bit

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 857 of 982 REJ09B0023-0400 23.7.2 Port G Data Register (PGDR) PGDR a register that inclu

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 858 of 982 REJ09B0023-0400 Table 23.8 Port G Data Register (PGDR) Read/Write Operations (PG13

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 859 of 982 REJ09B0023-0400 23.7.3 Port G Internal Block Diagram Pins PTG7 to PTG0 are mu

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 41 of 982 REJ09B0023-0400 Table 2.4 DSR Register Bits Bits Name (Abbreviation) Function 31 to

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 860 of 982 REJ09B0023-0400 23.8 Port H Port H comprises a 15-bit input/output port with the pi

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 861 of 982 REJ09B0023-0400 23.8.2 Port H Data Register (PHDR) PHDR is a 15-bit readable/

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 862 of 982 REJ09B0023-0400 Table 23.11 Port H Data Register (PHDR) Read/Write Operations PHnM

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 863 of 982 REJ09B0023-0400 23.9.2 Port J Data Register (PJDR) PJDR is a 13-bit readable/

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 864 of 982 REJ09B0023-0400

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 865 of 982 REJ09B0023-0400 Section 24 List of Registers This section gives info

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 866 of 982 REJ09B0023-0400 24.1 Register Addresses (by functional module, in order of

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 867 of 982 REJ09B0023-0400 Register Name Abbreviation Bit No. Address Module

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 868 of 982 REJ09B0023-0400 Register Name Abbreviation Bit No. Address Module Acce

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 869 of 982 REJ09B0023-0400 Register Name Abbreviation Bit No. Address Module

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 42 of 982 REJ09B0023-0400 DSR is assigned as a system register and the following load/store instructi

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 870 of 982 REJ09B0023-0400 Register Name Abbreviation Bit No. Address Module Acce

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 871 of 982 REJ09B0023-0400 Register Name Abbreviation Bit No. Address Module

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 872 of 982 REJ09B0023-0400 Register Name Abbreviation Bit No. Address Module Acce

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 873 of 982 REJ09B0023-0400 Register Name Abbreviation Bit No. Address Module

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 874 of 982 REJ09B0023-0400 Register Name Abbreviation Bit No. Address Module Acce

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 875 of 982 REJ09B0023-0400 Register Name Abbreviation Bit No. Address Module

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 876 of 982 REJ09B0023-0400 24.2 Register Bits Register addresses and bit names of the

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 877 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 878 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7Bit 30/22/14/6 Bit 29/2

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 879 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 43 of 982 REJ09B0023-0400 39S31 30 0–28 to +28 – 2–3139S32 31 0–223 to +223 – 139SS31 30 16 1516

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 880 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7Bit 30/22/14/6 Bit 29/2

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 881 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 882 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7Bit 30/22/14/6 Bit 29/2

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 883 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 884 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7Bit 30/22/14/6 Bit 29/2

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 885 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 886 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7Bit 30/22/14/6 Bit 29/2

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 887 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 888 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7Bit 30/22/14/6 Bit 29/2

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 889 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 44 of 982 REJ09B0023-0400 2.2.3 Memory Data Formats Memory data formats are classified into byte, wo

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 890 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7Bit 30/22/14/6 Bit 29/2

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 891 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 892 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7Bit 30/22/14/6 Bit 29/2

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 893 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 894 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7Bit 30/22/14/6 Bit 29/2

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 895 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 896 of 982 REJ09B0023-0400 24.3 Register States in Each Operating Mode Register Abbre

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 897 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset So

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 898 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset Softwar

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 899 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset So

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 45 of 982 REJ09B0023-0400 Table 2.5 Word Data Sign Extension This LSI's CPU Description

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 900 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset Softwar

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 901 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset So

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 902 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset Softwar

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 903 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset So

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 904 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset Softwar

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 905 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset So

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 906 of 982 REJ09B0023-0400

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 907 of 982 REJ09B0023-0400 Section 25 Electrical Characteristics The s

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 908 of 982 REJ09B0023-0400 25.1.1 Power-On Sequence Supply the power so that

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 909 of 982 REJ09B0023-0400 Table 25.2 Recommended Values for Power-On/O

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 46 of 982 REJ09B0023-0400 Table 2.7 T Bit This LSI's CPU Description Example of Other CPU CMP

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 910 of 982 REJ09B0023-0400 25.2 DC Characteristics Tables 25.3 and 25.4 list

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 911 of 982 REJ09B0023-0400 Table 25.3 DC Characteristics (2) [Except fo

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 912 of 982 REJ09B0023-0400 Item Symbol Min. Typ. Max. Unit Test Conditions

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 913 of 982 REJ09B0023-0400 Table 25.3 DC Characteristics (3) [I2C-Relat

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 914 of 982 REJ09B0023-0400 Table 25.3 DC Characteristics (5) [USB Transceive

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 915 of 982 REJ09B0023-0400 25.3 AC Characteristics Signals input to this

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 916 of 982 REJ09B0023-0400 25.3.1 Clock Timing Table 25.6 Clock Timing Condi

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 917 of 982 REJ09B0023-0400 tEXHtEXFtEXRtEXLtEXcycVIHVIHVIH1/2 VCC1/2 VCC

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 918 of 982 REJ09B0023-0400 VCC mintRESP/MWtRESP/MStOSC1VCCRESETPRESETMCKIO,In

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 919 of 982 REJ09B0023-0400 CKIO,Internal clockOscillation settling timeS

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 47 of 982 REJ09B0023-0400 Table 2.9 Absolute Address Referencing Type This LSI's CPU Exa

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 920 of 982 REJ09B0023-0400 25.3.2 Control Signal Timing Table 25.7 Control

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 921 of 982 REJ09B0023-0400 CKIOtRESPS/MStRESPS/MSRESETPRESETMtRESPW/MW F

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 922 of 982 REJ09B0023-0400 CKIO(HIZCNT = 1)BREQBACKA25 to A0, D31 to D0RD, RD

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 923 of 982 REJ09B0023-0400 25.3.3 AC Bus Timing Table 25.8 Bus Timing

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 924 of 982 REJ09B0023-0400 Bφ = 50 MHz* Item Symbol Min. Max. Unit Figure

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 925 of 982 REJ09B0023-0400 25.3.4 Basic Timing T1tAD1tAStCSD1T2tAD1tRWD1

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 926 of 982 REJ09B0023-0400 T1tAD1tAStCSD1TwT2tAD1tRWD1tRWD1tCSD1tRSDtRSDtAHtR

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 927 of 982 REJ09B0023-0400 T1tAD1tAStCSD1TwX T2tAD1tRWD1tRWD1tCSD1tRSDtR

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 928 of 982 REJ09B0023-0400 T1tAD1tAStCSD1TwX T2tAD1tRWD1tRWD1tCSD1tRSDtRSDtAH

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 929 of 982 REJ09B0023-0400 tAD1tAD1T1tRWD1tRSDtWED1tWED1tWED1tRDS1tRDS1t

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 48 of 982 REJ09B0023-0400 2.4 Instruction Formats 2.4.1 CPU Instruction Addressing Modes The followi

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 930 of 982 REJ09B0023-0400 Ta1Ta2Ta3T1TwTw T 2tAD1tCSD1tAD1tRWD1tRWD1tCSD1tRS

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 931 of 982 REJ09B0023-0400 Tm1tAD1tCSD1Tmd1wTmd1tAD1tRWD1tFMDtWDD1tFMDtF

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 932 of 982 REJ09B0023-0400 25.3.5 Bus Cycle of Byte-Selection SRAM ThtAD1tRS

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 933 of 982 REJ09B0023-0400 ThtAD1tRSDtRSDtRDS1tCSD1T1 Twx T2TftRWD1tWDD1

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 934 of 982 REJ09B0023-0400 25.3.6 Burst ROM Read Cycle T1tAD1tRSDtRDS3tRSDtC

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 935 of 982 REJ09B0023-0400 25.3.7 Synchronous DRAM Timing Tc1Tr Tcw Td1

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 936 of 982 REJ09B0023-0400 TrwTr Tc1 Tcw Td1 Tde TaptAD1tAD1tCSD1tAD1tRWD1tRW

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 937 of 982 REJ09B0023-0400 TC1 TC2Td1 Td2 Td3 Td4Tr Tc3 Tc4 TdetAD1tAD1t

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 938 of 982 REJ09B0023-0400 Tc1 Tc2Td1 Td2 Td3 Td4Tr Trw Tc3 Tc4 TdetAD1tAD1tC

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 939 of 982 REJ09B0023-0400 Trw lTr Tc1tAD1tCSD1tAD1tAD1tRWD1tRWD1tRWD1tC

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 49 of 982 REJ09B0023-0400 Addressing Mode Instruction Format Effective Address Calculation Meth

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 940 of 982 REJ09B0023-0400 Trw T c1 Tr wl Tr TrwtAD1tCSD1tAD1tAD1tRWD1tRWD1tR

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 941 of 982 REJ09B0023-0400 Tc2 Tc3 Tc4 TrwlTr Tc1tAD1tCSD1tAD1tAD1tAD1tA

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 942 of 982 REJ09B0023-0400 Tc2 Tc3 Tc4 TrwlTr Tc1Tr wtAD1tCSD1tAD1tAD1tAD1tAD

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 943 of 982 REJ09B0023-0400 Tc3 Tc4 TdeTr Tc2Td1 Td2 Td3 Td4Tc1tCSD1tAD1t

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 944 of 982 REJ09B0023-0400 Tc2 Tc4 TdeTc1 Tc3Td1 Td2 Td3 Td4 tCSD1tAD1tAD1tAD

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 945 of 982 REJ09B0023-0400 Tc3 Tc4 TdeTc2Td1 Td2 Td3 Td4Tc1TrTrwTptCSD1t

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 946 of 982 REJ09B0023-0400 CKIOA25 to A0CSnRD/WRA12/A11*1D31 to D0RASU/LCASU/

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 947 of 982 REJ09B0023-0400 Tc2 Tc3 Tc4Tnop Tc1tAD1tCSD1tAD1tAD1tAD1tAD1t

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 948 of 982 REJ09B0023-0400 Tc2 Tc3 Tc4TrTpwTp Tc1tAD1tCSD1tAD1tAD1tAD1tRWD1tR

Section 25 Electrical Characteristics Rev. 4.00 Sep. 14, 2005 Page 949 of 982 REJ09B0023-0400 Trc TrcTrrTpwTp TrctCSD1tAD1tAD1tRWD1tRWD1tRW