Renesas Emulator System M3T-MR100 Manual do Utilizador descarregar pdf (Página 23)

REJ05B1160-0101 Rev.1.01 February 2010 Page 23 of 43

M16C/62P Group, R32C/111 Group

Differences between M16C/62P and R32C/111 (100 pin ver.)

4.11 DMAC

The DMA controller is enhanced in the R32C/111. Table 4.29 to Table 4.31 respectively list the changes

on DMAC characteristics, settings, and associated SFRs.

Table 4.29 Comparison Chart: DMAC

Item M16C/62P R32C/111

DMAC-associated

registers

Allocated in SFRs Allocated in CPU internal register and

SFRs

Channels 2 4

Transfer memory

space

From a given address in a 1-Mbyte

space to a fixed address in the same

space or from a fixed address in a

1-Mbyte space to a given address in the

same space

From a given address in a 64-Mbyte

space (00000000h to 01FFFFFFh and

FE000000h to FFFFFFFFh) to another

given address in the same space

Maximum transfer

bytes

• 128 Kbytes

(when a 16-bit data is transferred)

• 64 Kbytes

(when a 8-bit data is transferred)

• 64 Mbytes

(when a 32-bit data is transferred)

• 32 Mbytes

(when a 16-bit data is transferred)

• 16 Mbytes

(when a 8-bit data is transferred)

Transfer unit 8 bits or 16 bits 8 bits, 16 bits, or 32 bits

Destination/source

addresses

Fixed address: one specified address

Forward address: address which is

incremented by a transfer unit on each

successive access. (Source address and

destination address cannot be both fixed

nor both icremented.)

Forward or fixed

Transfer cycles Value set in the DMAi transfer counter (i

= 0, 1) + 1

Value set in the DCTi register (i = 0 to 3)

DMA interrupt request

generation timing

When the DMAi transfer counter

underflows

When the DCTi register changes from

00000001h to 00000000h

Table 4.30 Comparison Chart: DMAC Settings

Item M16C/62P R32C/111

DMA request sources Selected by bits DSEL3 to DSEL0 in the

DMiSL register (i = 0, 1)

Selected by bits DSEL4 to DSEL0 in the

DMiSL register (i = 0 to 3) or

bits DSEL24 to DSEL20 in the DMiSL2

Transfer mode DMiCON register (i = 0, 1) DMDi register (i = 0 to 3)

Source address SARi register (i = 0, 1) DSAi register (i = 0 to 3) (reloaded value

in repeat transfer mode is set to the DSRi

Destination address DARi register (i = 0, 1) DDAi register (i = 0 to 3) (reloaded value

in repeat transfer mode is set to the

DDRi register)

Transfer cycles “Transfer cycles - 1” is set to the TCRi

Number of transfer cycles is set to the

DCTi register (i = 0 to 3) (reloaded value

in repeat transfer mode is set to the

DCRi register)

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 42 43

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