Renesas H8S/2111B Manual do Utilizador descarregar pdf (Página 34)

■ Features for H8S/2400 Series

• Up to 20MHz, 16 bit CISC CPU with

Hardware Multiply Accumulate Block

(H8S/2600 CPU)

• 8 power-down modes for

reducing power consumption

• 32kHz sub-clock oscillator

• Support Smart Card interface

conforming to ISO/IEC 7816-3

■ Features for H8S/2500 Series

• Up to 26MHz, 16 bit CISC CPU

• 6 power-down modes for reducing

power consumption

• 32kHz sub-clock oscillator

• Built-in Data Transfer Controller

(DTC) with maximum of 85 channels

• Up to 2-channel Controller Area Network

(CAN v2.0) controller

• Support Smart Card interface

conforming to ISO/IEC 7816-3

• Dual 3V and 5V I/O functions supported

■

Applications

H8S/2400 Series: LCD Monitor, LCD-TV,

Plasma-TV, projectors, home electronics

H8S/2500 Series: Audio, automotive audio

H8S/2400 and H8S/2500 Series

2437 Group

256KB ROM; 16KB SRAM

2556 Group

512KB ROM

32KB SRAM

2506 Group

384-512KB ROM

24-32KB SRAM

2552 Group

384-512KB ROM

24-32KB SRAM

144 to 176 PINS

3V to 5V 3V

128 PINS

E10A supported (JTAG debug)

CAN supported

H8S/2400/2500 Series Line-up

H8S

CPU:

20MHz

INTC

ADC:

10-bit x 16 ch

BSC

RAM:

32KB

8-bit

Timer:

4 ch

DAC:

8-bit x 2 ch

PC Break

Controller

Flash

ROM:

512KB

Watchdog

Timer

16-bit TPU

x 6 ch

SCI

x 5 ch

DTC

CAN

C x 2 ch

Sub

Clock

PLL

External

Bus

H8S/2556 Block Diagram

1 2 ... 29 30 31 32 33 34 35 36 37 38 39 ... 45 46

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