Renesas M16C/30P Manual do Utilizador descarregar pdf (Página 54)

M16C/30P Group 5. Electrical Characteristics

Rev.1.22 Mar 30, 2007 Page 52 of 53

REJ03B0088-0122

Figure 5.13 Timing Diagram (5)

BCLK

CSi

td(BCLK−CS)

30ns.max

ADi

td(BCLK−AD)

30ns.max

ALE

30ns.max

th(BCLK−ALE)

−4ns.min

RD

30ns.max

th(BCLK−RD)

0ns.min

th(BCLK−AD)

0ns.min

th(BCLK−CS)

0ns.min

Hi−Z

DBi

tsu(DB−RD)

50ns.min

th(RD−DB)

0ns.min

tcyc

BHE

Read timing

WR,WRL,

WRH

30ns.max

th(BCLK−WR)

0ns.min

BCLK

CSi

td(BCLK−CS)

30ns.max

ADi

td(BCLK−AD)

30ns.max

ALE

30ns.max

td(BCLK−ALE)

th(BCLK−ALE)

−4ns.min

th(BCLK−AD)

0ns.min

th(BCLK−CS)

0ns.min

tcyc

th(WR−AD)

BHE

td(BCLK−DB)

40ns.max

4ns.min

th(BCLK−DB)

td(DB−WR)

(0.5

× tcyc−40)ns.min

(0.5

× tcyc−10)ns.min

th(WR−DB)

DBi

Write timing

td(BCLK−ALE)

td(BCLK−RD)

(0.5 × tcyc−10)ns.min

td(BCLK−WR)

0ns.min

th(RD−AD)

tac2(RD−DB)

Hi−Z

Memory Expansion Mode, Microprocessor Mode

(for 1-wait setting and external area access)

(1.5 × tcyc−60)ns.max

tcyc=

1

f(BCLK)

VCC1=VCC2=3V

Measuring conditions

· V

CC1=VCC2=3V

· Input timing voltage : V

IL=0.6V, VIH=2.4V

· Output timing voltage : V

OL=1.5V, VOH=1.5V

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