Renesas User System Interface Cable HS36049ECH61H Manual do Utilizador descarregar pdf (Página 15)

Peripherals

On-chip Peripherals: Computer I/F

H8S/21xx

Flash

BIOS

Embedded

Controller

Super I/O

KBC SP

PP FDC

LPC

Host

PCI/Host Bus

■ Low-Pin-Count (LPC) Interface

• A popular interface to communicate

to PC chip set used in notebooks

and PC servers

• Performs serial data and address

transfer using 33MHz clock

• Supports I/O read and write cycles

• Supports serial interrupt

on single line

• Supports power-down mode

• Reduced pin count

H8S

Keyboard

Scan

Matrix

Output

Inputs

■ Keyboard Buffer Controller (KBC)

• Conforms to PS/2 specification

• Error detection, parity error and

stop bit monitoring

• Five host interrupt requests

■ On-chip Bus Controller (BSC)

• Provides glueless interface with external devices

• Supports basic SRAM, burst-ROM interface

• Manages external, addressable

16MB region (8 different areas)

• Bus specification can be set

independently for each region

• Selectable 8- or 16-bit bus width

• Choice of 0 to 7 programmable

wait-state access

• Supports direct connection to

SDRAM on selected devices

• Includes a bus arbiter for

bus mastership arbitration

• Burst ROM interface

can be set for area 0

• External write cycle and internal

access can be executed in parallel

• Idle-cycle insertion capability

LPC

Diagram

KBC

Diagram

Bus

controller

External bus control signals

Internal control signals

Internal data bus

Wait

controller

BCR

WSCR

Bus mode signal

Bus arbiter

DTC bus acknowledge signal

CPU bus acknowledge signal

DTC bus request signal

CPU bus request signal

WAIT

BSC Diagram

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 49 50

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