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V850E2/MN4 A/D Converter Control

R01AN0923EJ0100 Rev.1.00 Page 15 of 26

Feb 13, 2012

Figure 4.10 ADCAnCTL0 Register Format (2/2)

Setting example

ADCA0CTL0 = 0x0080;

/* ADCATERR which is generated by ADCA0LCR register overwrite admitted;

ADCATERR which is generated by ADCA0DBiCR register overwrite admitted;

ADCATERR which is generated by ADCA0CmCR register overwrite admitted;

A/D Controller enable ON;

1-time conversion of CG0 scanlist(channel 00) */

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