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Rev. 1.1

R8C25 QuickDesign Guide.doc Page 8 of 10 12/23/2007

normally used, if an ID code is not intentionally written to these locations

the ID code will typically be all 00’s or all FF’s

8.2.3. Modifying the Shared Features in Vector Table

The High Performance Embedded Workshop IDE has provisions to allow

setting both the OSFR register and ID code values. These options can be

found by going to the Build >> Renesas M16C Standard Toolchain then

LMC tabs. The options will be under the “Code” category.

8.3. The Relocatable vector table

The relocatable vector table contains the vector address for the peripheral

interrupts and software interrupts. The start location (lowest address) of the vector

table is pointed to by the value in the INTB core register. A few other features of

the peripheral vectors:

• Most peripherals have individual interrupts or individual interrupts for

each major function (e.g. UART Rx and UART Tx). This simplifies

ISR routine writing

• The peripheral interrupts can be disabled by clearing the interrupt

enable bit in the core, (I bit). This will globally disable all maskable

interrupts

• Each peripheral can also be individually enabled or disable by

controlling the interrupt priority level (IPL) in the associated interrupt

control register for that peripheral. If the IPL can be set from 0 – 7.

Setting the IPL to 0 will disable the interrupt from that device and

setting the IPL to 7 will give it the highest priority

8.4. Interrupt Sequence

When a peripheral interrupt occurs the device sets the Interrupt Request (IR) bit in the

associated interrupt control register for that peripheral. This will occur whether the

interrupts for that device are enabled or not. If the device interrupts are enabled,

global interrupts are enabled and the IPL of the device is higher than the current IPL

of the core (which is 0 unless another interrupt is in the process of being serviced) the

following interrupt sequence is followed:

I Interrupt Sequence

Request Generation

1. The peripheral device condition generates an interrupt

2. The Request (IR) bit in the interrupt control register for that device is set

(regardless of the status of the IPL or I flag)

3. If global interrupts are enabled and IPL of the device is higher than the current

MCU IPL (stored in the flag register and set to 0 unless there is an interrupt

currently being serviced or set to a value by software) the interrupt is accepted

Interrupt Service Response

4. The current status of the flag register is stored in hidden register in core

5. I flag is set

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