MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12
Fig. 5. Memory map of special function register 2 (SFR2) (1)
210
16
211
16
212
16
213
16
214
16
215
16
216
16
217
16
218
16
219
16
21A
16
21B
16
21C
16
21D
16
21E
16
21F
16
200
16
201
16
202
16
203
16
204
16
205
16
206
16
207
16
208
16
209
16
20B
16
20C
16
20D
16
20E
16
20F
16
20A
16
PWM mode register 1 (PN)
Timer 5 (TM5)
Sync pulse counter register (SYC)
Data slicer control register 3 (DSC3)
PWM2 register (PWM2)
PWM6 register (PWM6)
PWM4 register (PWM4)
PWM5 register (PWM5)
PWM0 register (PWM0)
PWM1 register (PWM1)
Interrupt interval determination register (RI)
Interrupt interval determination control register (RE)
Serial I/O mode register (SM)
Serial I/O register (SIO)
Clock source control register (CS)
Extra font color register (EC)
Window H register 1 (WH1)
Window L register 1 (WH1)
Window H register 2 (WH2)
Window L register 2 (WH2)
Clock run-in detect register (CRD3)
Clock run-in register (CR3)
Timer 6 (TM6)
Border color register (FC)
b7
b0
SYC0
FC2
b7
b0
07
16
?000000?
00
16
0? ? ?00 00
??? ?? ?? ?
PWM3 register (PWM3)
PWM mode register 2 (PW)
Raster color register (RC)
I/O polarity control register (PC)
?
?
?
?
?
?
?
FF
16
?
00
16
PW0PW1PW2PW3PW4PW5PW6
ENABLE
POL
SYC1SYC2SYC3SYC4SYC5
DSC30DSC31DSC32DSC37 DSC35
RE0RE1RE2RE3RE4RE5
INT3
POL
AD/INT3
SEL
RE1RE2RE3RE4RE5
INT3
POL
AD/INT3
SEL
SM0RE1RE2RE3SM4RE5
INT3
POL
AD/INT3
SEL
SM1SM2SM3SM5
PC0RE1RE2RE3PC4RE5
INT3
POL
AD/INT3
SEL
PC1PC2PC3PC5PC6PC7
RE1RE2RE3RE5
INT3
POL
AD/INT3
SEL
CS0CS4 CS1CS2CS3CS5CS6
RC0RE1RE2RE3RC4RE5
INT3
POL
AD/INT3
SEL
RC1RC2RC3RC5RC6RC7
RE1RE2RE3RE5
INT3
POL
AD/INT3
SEL
FC0FC1FC3FC4
WH20WH21
WL20WL21
?
?
?
0? ? ?00 00
010000 00
???
??????
?????
??
?0 ???? ??
?
?
000000 00
?
00
16
DSC36 DSC34 DSC33
? ?? ?0 ?? 0
? 00 00 00 0
0 ?? ?? ?? ?
CRD31CRD32CRD33CRD34CRD35
0 00 00 00 0
1
: “1” immediately after reset
: Fix this bit to “0” ( do not write “1”)
: Nothing is allocated
■SFR2 area (addresses 200
16
to 21F
16
)
Address Register
: undefined immediately after reset
?
Bit allocation State immediately after reset
0
: “0” immediately after reset
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