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MITSUBISHI MICROCOMPUTERS

M37271MF-XXXSP

M37271EF-XXXSP, M37271EFSP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

RESET CIRCUIT

The M37271MF-XXXSP is reset according to the sequence shown

in Figure 90. It starts the program from the address formed by using

the content of address FFFF16 as the high-order address and the

content of the address FFFE16 as the low-order address, when the

______

RESET pin is held at “L” level for 2 µs or more while the power source

voltage is 5 V ± 10 % and the oscillation of a quartz-crystal oscillator

or a ceramic resonator is stable and then returned to “H” level. The

internal state of microcomputer at reset are shown in Figures 3 to 7.

An example of the reset circuit is shown in Figure 89.

The reset input voltage must be kept 0.9 V or less until the power

source voltage surpasses 4.5 V.

Fig. 90. Reset sequence

Fig. 89. Example of reset circuit

RESET

Internal RESET

SYNC

Address

Data

32768 count of X

clock cycle (Note 3)

Reset address from the vector table

? ?

01, S

01, S-1

01, S-2

FFFE FFFF

? ? ? ? ?

Notes 1 : f(X

) and f(φ) are in the relation : f(X

) = 2·f (φ).

2 : A question mark (?) indicates an undefined state that

depends on the previous state.

3 : Immediately after a reset, timer 3 and timer 4 are

connected in hardware. At this time, “FF

” is set

in timer 3 and “07

” is set to timer 4. Timer 3 counts down

with f(X

)/16, and reset state is released by the timer 4

overflow signal.

Power source voltage 0 V

Reset input voltage 0 V

4.5 V

0.9 V

Poweron

Vcc

RESET

Vss

M37271MF-XXXSP

0.1 µF

M51953AL

1 2 ... 74 75 76 77 78 79 80 81 82 83 84 ... 97 98

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