MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
24
12
3
456 78
1
0000000
12
100000
1000000
1
1234567
1
VREF
2
VREF
512
–
VREF
2
VREF
4
VREF
512
–
±
V
REF
2
VREF
4
VREF
8
VREF
512
±
00000000
Contents of A-D conversion register
Reference voltage (V
ref) [V]
0
A-D conversion start
1st comparison start
3rd comparison start
8th comparison start
2nd comparison start
Digital value corresponding to
analog input voltage.
A-D conversion completion
(8th comparison completion)
VREF
2
VREF
4
VREF
8
±
V
REF
512
VREF
256
.......
Value determined by mth (m = 1 to 8) resultm
.....
VREF
256
✕ (n – 0.5)1
to
255
0
Note: VREF indicates the voltage of internal VCC.
Fig. 17. Changes in A-D conversion register and comparison voltage during A-D conversion
(6) Conversion Method
➀ Set bit 7 of the interrupt interval determination control register (ad-
dress 0212
16) to “1” to generate an interrupt request at comple-
tion of A-D conversion.
➁ Set the A-D conversion • INT3 interrupt request bit to “0” (even
when A-D conversion is started, the A-D conversion • INT3 inter-
rupt bit is not set to “0” automatically).
➂ When using A-D conversion interrupt, enable interrupts by setting
A-D conversion • INT3 interrupt request bit to “1” and setting the
interrupt disable flag to “0.”
➃ Set the V
CC connection selection bit to “1” to connect VCC to the
resistor ladder.
➄ Select analog input pins by setting the analog input selection bit of
the A-D control register.
➅ Set the A-D conversion completion bit to “0.” This write operation
starts the A-D conversion. Do not read the A-D conversion regis-
ter during the A-D conversion.
➆ Verify the completion of the conversion by the state (“1”) of the
A-D conversion completion bit, that (“1”) of A-D conversion• INT3
interrupt bit, or the occurrence of an A-D conversion interrupt.
➇ Read the A-D conversion register to obtain the conversion results.
Note : When the ladder resistor is disconnect from V
CC, set the VCC
connection selection bit to “0” between steps ➆ and ➇.
Table 2. Expression for V
ref and VREF
A-D conversion register contents “n”
(decimal notation)
V
ref (V)
(7) Internal Operation
At the time when the A-D conversion starts, the following operations
are automatically performed.
➀ The A-D conversion register is set to “00
16.”
➁ The most significant bit of the A-D conversion register becomes
“1, ” and the comparison voltage “V
ref” is input to the comparator.
At this point, V
ref is compared with the analog input voltage “VIN .”
➂ Bit 7 is determined by the comparison result as follows.
When V
ref < VIN : bit 7 holds “1”
When V
ref > VIN : bit 7 becomes “0”
With the above operations, the analog value is converted into a digi-
tal value. The A-D conversion terminates in a maximum 50 machine
cycles (12.5µs at f(X
IN) = 8 MHz) after it starts, and the conversion
result is stored in the A-D conversion register.
An A-D conversion interrupt request occurs at the same time of A-D
conversion completion, the A-D conversion • INT3 interrupt request
bit becomes “1.” The A-D conversion completion bit also becomes
“1.”
:
±
–
±
±
±
–
0
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