Renesas PROM Programming Adapters PCA7438F-64A Especificações descarregar pdf (Página 57)

REVISION HISTORY 38C1 GROUP DATA SHEET

Rev. Date Description

Page Summary

(1/2)

1.0 01/16/02

2.0 03/28/02

2.1 05/09/02

First Edition

1 FEATURES; • Interrupts and • Power dissipation revised.

4 PIN DESCRIPTION; VL1–VL3 0 ≤ VL1 ≤ VL2 ≤ VL3 → 0 ≤ VL1 ≤ VL2 < VL3

6 Table 2; Date revised. Jan. → Mar.

10 Fig. 7; Bits 3 and 6 Description added.

12 Fig. 10; Address 000716 Port P3 direction register (P3D)

Address 000816 “ADKEY pin selection” added.

14 Table 5; Note 2 revised.

INTERRUPTS; fourteen sources → thirteen sources, eight internal → seven internal

20 Fig. 17; PULL register A Bit 2 = “1” → PULL register Bit 3 = “1”

27 ● A/D Converter description added.

28 ADKEY Control Circuit; Description revised all.

Fig. 27; Figure title and note “pin” added.

32 Common Pin and Duty Ratio Control; Description added.

Table 9; Note revised.

36 Fig. 35; Bits 0 and 1 Functional description revised.

● RRF register; Description revised.

41 Fig. 43; Low-speed mode CM3 = 1 → CM3 = * (Note 9)

44 (3) line 5; voltage and temperature → voltage or/and temperature

47 to 54 ELECTRICAL CHARACTERISTICS ; Most contents revised.

47 Table 12; VCC revised, VL3 and Notes added.

49 Table 14; Note revised.

51 Table 16; Most contents revised.

52 Table 17; Added.

Table 18; Most contents revised.

53 Table 20; “(2.2 to 4.0 V for One Time PROM version)” added.

54 Table 22; “(2.2 to 4.0 V for One Time PROM version)” added.

56 PACKAGE OUTLINE revised.

6 Fig. 4 and Table 2; Revised.

10 [CPU Mode Register (CPUM)]; Description revised.

16 Fig. 13; Revised.

22 ● Timer X, ■ Note on count source selection bit; Description revised.

25 Fig. 23; Note revised.

39 Clock generating circuit; Note revised.

47 Table 12;

“H” input voltage ADKEY0–ADKEY3, “L” input voltage ADKEY0–ADKEY3 eliminated.

49 Table 14; Note 3 added.

Table 17; “H” input voltage ADKEY0–ADKEY3, “L” input voltage ADKEY0–ADKEY3 added.

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