Renesas H8S/2111B Manual do Utilizador descarregar pdf (Página 273)

100

101

Rev. 1.00, 05/04, page 239 of 544

Bit Bit Name

Initial

Value R/W Description

2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous

mode)

When this bit is set to 1, the multiprocessor

communication function is enabled. The PE bit and O/E

bit settings are invalid in multiprocessor mode.

CKS1

CKS0

R/W

Clock Select 1,0

These bits select the clock source for the on-chip baud

rate generator.

00: φ clock (n = 0)

01: φ/4 clock (n = 1)

10: φ/16 clock (n = 2)

11: φ/64 clock (n = 3)

For the relation between the bit rate register setting

and the baud rate, see section 12.3.9, Bit Rate

n in BRR.

12.3.6 Serial Control Register (SCR)

SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt

requests, and selection of the transfer clock source. For details on interrupt requests, refer to

section 12.7, Interrupt Sources.

Bit Bit Name

Initial

Value R/W Description

7 TIE 0 R/W Transmit Interrupt Enable

When this bit is set to 1, a TXI interrupt request is

enabled.

6 RIE 0 R/W Receive Interrupt Enable

When this bit is set to 1, RXI and ERI interrupt requests

are enabled.

5 TE 0 R/W Transmit Enable

When this bit is set to 1, transmission is enabled.

4 RE 0 R/W Receive Enable

When this bit is set to 1, reception is enabled.

1 2 ... 268 269 270 271 272 273 274 275 276 277 278 ... 581 582

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