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Rev. 1.00, 05/04, page 521 of 544

22.3.1 Clock Timing

Table 22.5 shows the clock timing. The clock timing specified here covers clock (φ) output and

clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times.

For details on external clock input (EXTAL pin and EXCL pin) timing, see section19, Clock Pulse

Generator.

Table 22.5 Clock Timing

Condition: V

= 3.0 V to 3.6 V, V

B = 3.0 V to 5.5 V, V

= 0 V, φ = 4 MHz to maximum

operating frequency, T

= –20 to +75°C

Condition

10 MHz

Item Symbol

Min. Max.

Unit Reference

Clock cycle time t

cyc

100 250 ns

Clock high pulse width t

30 — ns

Clock low pulse width t

30 — ns

Clock rise time t

— 20 ns

Clock fall time t

— 20 ns

Figure 22.5

Oscillation settling time at reset (crystal) t

OSC1

20 — ms

Oscillation settling time in software

standby (crystal)

OSC2

8 — ms

External clock output stabilization delay

time

DEXT

500 — µs

Figure 22.6

Figure 22.7

1 2 ... 550 551 552 553 554 555 556 557 558 559 560 ... 581 582

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