Renesas PROM Programming Adapter PCA7435FPG02 Especificações descarregar pdf (Página 15)

7534 Group

Rev.3.00 Oct 23, 2006 page 15 of 53

REJ03B0099-0300

Fig. 15 Block diagram of ports (2)

(9) Ports P3

, P3

Data bus

Port latch

Pull-up control

INT interrupt input

(7) Ports P2

–P2

Analog input pin selection bit

A/D converter input

Data bus

Port latch

(8) Ports P3

–P3

Data bus

Port latch

Pull-up control

(6) Ports P1

CNTR

interrupt input

Direction register

Data bus

Port latch

Pulse output mode

Timer output

/INT

input

level selection bit

(10) Ports P1

Data bus

Port latch

Direction register

: P1

, P1

, P3

input levels are switched to the CMOS/TTL level by the port P1P3 control register.

When the TTL level is selected, there is no hysteresis characteristics.

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Renesas PROM Programming Adapter PCA7435FPG02 Especificações Página 15