Renesas SH7781 Informações Técnicas descarregar pdf (Página 19)

Section 2 Software Specifications when Using the SH7781

Rev. 2.00 Jan. 28, 2008 Page 11 of 32

REJ10J1422-0200

8. Cache Operation during User Program Break

When cache is enabled, the emulator accesses the memory by the following methods:

⎯ At memory write: Writes through the cache, then issues a single write to outside. The LRU

is not updated.

⎯ At memory read: Reads memory from the cache. The LRU is not updated.

Therefore, when memory read or write is performed during user program break, the cache state

does not change.

⎯ At breakpoint set: Disables the instruction cache.

9. Port

The AUD pin is multiplexed as shown in table 2.2.

Table 2.2 Multiplexed Functions

Function 1 Function 2

Port 1 FALE AUDCK

_FCE AUDSYNC

FD0 AUDATA0

FD1 AUDATA1

FD2 AUDATA2

FD3 AUDATA3

Port 2 _DRAK2/_CE2A AUDCK

_DRAK3/_CE2B AUDSYNC

_DREQ2/_INTB AUDATA0

_DREQ3/_INTC AUDATA1

_DACK2/_MRESETOUT AUDATA2

_DACK3/_IRQOUT AUDATA3

Note: Function 1 can be used when the AUD pins of the device are not connected to the

emulator. When the AUD trace is enabled, the emulator changes settings so that function 2

is forcibly used.

10. UBC

When [User] is specified in the [UBC mode] list box in the [Configuration] dialog box, the

UBC can be used in the user program.

Do not use the UBC in the user program as it is used by the emulator when [EML] is specified

in the [UBC mode] list box in the [Configuration] dialog box.

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