Renesas R8C/15 Manual do Utilizador descarregar pdf (Página 3)

Rev.0.10 Mar 4, 2004 Page 3 of 16

REJ03B0078-0010Z

Under development

R8C/15 Group 1. Overview

Preliminary specification

Specications in this manual are tentative and subject to change.

1.3 Block Diagram

Figure 1.1 shows this MCU block diagram.

Figure 1.1 Block Diagram

R8C/Tiny series CPU core

1 2

Timer

Timer X (8 bits)

Timer Z (8 bits)

Timer C (16 bits)

A-D converter

(10 bits

× 4 channels)

System clock generator

XIN-XOUT

High-speed ring oscillator

Low-speed ring oscillator

UART or

Clock synchronous serial I/O

(8 bits

× 1 channel)

Memory

Watchdog timer

(15 bits)

ROM

(1)

RAM

(2)

Multiplier

R0H R0L

R1H

R1L

USP

ISP

INTB

FLG

I/O port Port P1

Port P3 Port P4

Notes:

1. ROM size depends on MCU type.

2. ROM size depends on MCU type.

Chip-select clock synchronous

serial I/O

(8 bits

× 1 channel)

1 2 3 4 5 6 7 8 ... 17 18

PRELIMINARY 1
1.2 Performance Outline 2
1.3 Block Diagram 3
°C to 85 °C 4
1.5 Pin Configuration 5
R8C/15 Group 6
1.6 Pin Description 7
Under development 8
2.8.10 Reserved Area 10
Figure 3.1 Memory Map 11
REJ03B0078-0010Z 12
Rev. Date 17
Description 17
Page Summary 17
RENESAS SALES OFFICES 18

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