Renesas R8C/15 Manual do Utilizador descarregar pdf (Página 8)

Rev.0.10 Mar 4, 2004 Page 8 of 16

REJ03B0078-0010Z

Under development

R8C/15 Group 2. Central Processing Unit (CPU)

Preliminary specification

Specications in this manual are tentative and subject to change.

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB

comprise a register bank. There are two register banks.

Figure 2.1 Central Processing Unit Register

b31

b15 b8b7

Data registers

(1)

Address registers

(1)

R0H (R0's high bits)

INTBH

b15b19

INTBL

Frame bass registers

(1)

The upper 4 bits of INTB are INTBH and

the lower 16 bits of INTB are INTBL.

Interrupt table register

b19

USP

Program counter

ISP

User stack pointer

Interrupt stack pointer

Static base register

FLG

Flag register

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

Reserved area

IPL

DZSBOIU

b15

NOTES:

1. These registers comprise a register bank. There are two register banks.

R0L (R0's low bits)

R1H (R1's high bits) R1L (R1's low bits)

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 17 18

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