Renesas Single-Chip Microcomputer M34519T-MCU Especificações Página 25
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Generic Name
V850ES/JH3-E
Part No.
µPD70F3778 µPD70F3779 µPD70F3780 µPD70F3781 µPD70F3782 µPD70F3783
CPU name
V850ES
CPU performance (Dhrystone)
103 MIPS (@ 50 MHz)
Internal ROM
256 KB (ash) 384 KB (ash) 512 KB (ash) 384 KB (ash) 512 KB (ash)
Internal RAM
76 KB (including 16 KB of data-only RAM) 124 KB (including 64 KB of data-only RAM)
External bus
interface
Bus type
Multiplexed/separate
Address bus
22 bits
Data bus
8/16 bits
Chip select signal
3
Memory controller
SRAM, etc.
Interrupt sources Internal
78 (Including one NMI) 82 (Including one NMI)
External
22 (22)*
1
(Including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
6 ch
16-bit timer/event counter (TAB)
×
2 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer
1 ch
Serial interface
UART (LIN compatible)/CSI
×
1 ch
UART (LIN compatible)/CSI (with FIFO)
×
1 ch
UART (with FIFO)/CSI
×
2 ch*
2
UART (LIN compatible)/CSI/I
2
C
×
2 ch
UART (LIN compatible)/CSI (with FIFO)*
3
/I
2
C
×
1 ch
CSI (with FIFO)*
3
×
1 ch
UART (LIN compatible)/I
2
C
×
1 ch
UART (LIN compatible)/CSI
×
1 ch
UART (LIN compatible)/CSI (with FIFO)
×
1 ch
UART (with FIFO)/CSI
×
2 ch*
2
UART (LIN compatible)/CSI/I
2
C
×
2 ch
UART (LIN compatible)/CSI (with FIFO)*
3
/I
2
C
×
1 ch
CSI (with FIFO)*
3
×
1 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
A/D converter
10 bits
×
10 ch
D/A converter
-
DMA controller
4 ch
Ports I/O
84
Input
-
Debug control unit
Provided (RUN/break)
USB controller
USB 2.0 function (full-speed)
×
1 ch
Ethernet controller
1 ch
Other peripheral functions
Motor control, real-time counter (RTC), real-time output, LVI/clock monitor, CRC, RAM retention ag
Operating frequency
When using main clock: 24 to 50 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V)
Package
128-pin LQFP (14
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
*1. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode. *2. One channel is assigned to two different pins. *3. The same channel is assigned to two different pins.
Generic Name
V850ES/JJ3-E
Part No.
µPD70F3784 µPD70F3785 µPD70F3786
CPU name
V850ES
CPU performance (Dhrystone)
103 MIPS (@ 50 MHz)
Internal ROM
512 KB (ash)
Internal RAM
76 KB (including 16 KB of data-only RAM) 124 KB (including 64 KB of data-only RAM)
External bus
interface
Bus type
Multiplexed/separate
Address bus
24 bits
Data bus
8/16 bits
Chip select signal
2
Memory controller
SRAM, etc.
Interrupt sources Internal
84 (Including one NMI) 88 (Including one NMI)
External
27 (27)*
1
(Including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
6 ch
16-bit timer/event counter (TAB)
×
2 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer
1 ch
Serial interface
UART (LIN compatible)/CSI
×
3 ch
UART (LIN compatible)/CSI (with FIFO)
×
1 ch
UART (with FIFO)/CSI
×
2 ch*
2
UART (LIN compatible)/CSI/I
2
C
×
2 ch
UART (LIN compatible)/CSI (with FIFO)*
3
/I
2
C
×
1 ch
CSI (with FIFO)*
3
×
1 ch
I
2
C
×
1 ch
UART (LIN compatible)/I
2
C
×
1 ch
UART (LIN compatible)/CSI
×
3 ch
UART (LIN compatible)/CSI (with FIFO)
×
1 ch
UART (with FIFO)/CSI
×
2 ch*
2
UART (LIN compatible)/CSI/I
2
C
×
2 ch
UART (LIN compatible)/CSI (with FIFO)*
3
/I
2
C
×
1 ch
CSI (with FIFO)*
3
×
1 ch
I
2
C
×
1 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
A/D converter
10 bits
×
12 ch
D/A converter
-
DMA controller
4 ch
Ports I/O
100
Input
-
Debug control unit
Provided (RUN/break)
USB controller
USB 2.0 function (full-speed)
×
1 ch
Ethernet controller
1 ch
Other peripheral functions
Motor control, real-time counter (RTC), real-time output, LVI/clock monitor, CRC, RAM retention ag
Operating frequency
When using main clock: 24 to 50 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V)
Package
144-pin LQFP (20
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
*1. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode. *2. One channel is assigned to two different pins. *3. The same channel is assigned to two different pins.
3 V Operation 3 V Operation
Generic Name
V850ES/JC3-H
Part No.
µPD70F3809
µPD70F3810 µPD70F3811 µPD70F3812 µPD70F3813 µPD70F3814 µPD70F3815 µPD70F3816 µPD70F3817 µPD70F3818 µPD70F3819
CPU name
V850ES
CPU performance (Dhrystone)
98 MIPS (@ 48 MHz)
Internal ROM
16 KB (ash) 32 KB (ash) 64 KB (ash) 128 KB (ash) 256 KB (ash) 16 KB (ash) 32 KB (ash) 64 KB (ash) 128 KB (ash) 256 KB (ash)
Internal RAM
8 KB 16 KB 24 KB 8 KB 16 KB 24 KB
External bus
interface
Bus type
-
Address bus
-
Data bus
-
Chip select signal
-
Memory controller
-
Interrupt sources Internal
52 (Including one NMI) 54 (Including one NMI)
58 (Including one NMI)
External
10 (10)* (Including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
4 ch
16-bit timer/event counter (TAB)
×
1 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer
1 ch
Serial interface
UART (LIN compatible)/CSI
×
2 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
CSI
×
1 ch
UART (LIN compatible)/CSI
×
2 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
CSI
×
1 ch
UART (LIN compatible)/I
2
C
×
1 ch
UART
(LIN compatible)/CSI
×
2 ch
UART
(LIN compatible)/CSI/I
2
C
×
1 ch
CSI
×
1 ch
UART
(LIN compatible)/I
2
C/CAN
×
1 ch
A/D converter
10 bits
×
5 ch 10 bits
×
6 ch
D/A converter
-
8 bits
×
1 ch
DMA controller
4 ch
Ports I/O
25 32
Input
-
Debug control unit
Provided (RUN/break)
USB controller
USB 2.0 function (full-speed)
×
1 ch
Other peripheral functions
Real-time counter (RTC), real-time output, LVI/clock monitor, CRC, RAM retention ag
Operating frequency
When using main clock: 24 to 48 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V)
Package
40-pin WQFN (6
×
6 mm) 48-pin LQFP (7
×
7 mm), 48-pin WQFN (7
×
7 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/JE3-H
Part No.
µPD70F3820 µPD70F3821 µPD70F3822 µPD70F3823 µPD70F3824 µPD70F3825
CPU name
V850ES
CPU performance (Dhrystone)
98 MIPS (@ 48 MHz)
Internal ROM
16 KB (ash) 32 KB (ash) 64 KB (ash) 128 KB (ash) 256 KB (ash)
Internal RAM
8 KB 16 KB 24 KB
External bus
interface
Bus type
-
Address bus
-
Data bus
-
Chip select signal
-
Memory controller
-
Interrupt sources Internal
52 (Including one NMI) 58 (Including one NMI)
External
11 (11)*
1
(Including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
4 ch
16-bit timer/event counter (TAB)
×
1 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer
1 ch
Serial interface
UART (LIN compatible)/CSI
×
2 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
CSI
×
1 ch
UART (LIN compatible)/I
2
C
×
1 ch
UART (LIN compatible)/CSI
×
2 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
CSI
×
1 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
A/D converter
10 bits
×
10 ch
D/A converter
8 bits
×
1 ch
DMA controller
4 ch
Ports I/O
45
Input
-
Debug control unit
Provided (RUN/break)
USB controller
USB 2.0 function (full-speed)
×
1 ch
Other peripheral functions
Motor control, real-time counter (RTC), real-time output, LVI/clock monitor, CRC, RAM retention ag
Operating frequency
When using main clock: 24 to 48 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V)
Package
64-pin LQFP (10
×
10 mm), 64-pin FBGA (6
×
6 mm)*
2
, 64-pin WQFN (9
×
9 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
*1. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
*2. µPD70F3824 only
Low-End Lineup (4/10)Low-End Lineup (3/10)
48 49
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
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