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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
53
Notes 1 : When the P4
5/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is 0.
2 : X
OUT and XCOUT pins are excluded.
Serial I/O clock output H pulse width
Serial I/O clock output L pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
140
30
30
30
30
Symbol Parameter
Limits
Min.
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
c(S
CLK
)
/230
t
c(S
CLK
)
/230
30
10
10
Typ.
Max.
t
wH(SCLK)
twL(SCLK)
t
d(S
CLK
T
X
D)
t
v(S
CLK
T
X
D)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Table 22. Switching characteristics 1 (Standard, One time PROM version)
(V
CC = 4.0 to 5.5 V, VSS = 0 V, Ta = 20 to 85°C, unless otherwise noted.)
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is 0.
2 : X
OUT and XCOUT pins are excluded.
Serial I/O clock output H pulse width
Serial I/O clock output L pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
350
50
50
50
50
Symbol Parameter
Limits
Min.
t
c(S
CLK
)
/250
t
c(S
CLK
)
/250
30
20
20
Max.
twH(SCLK)
twL(SCLK)
t
d(S
CLK
T
X
D)
t
v(S
CLK
T
X
D)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Typ.
Table 23. Switching characteristics 2 (Standard, One time PROM version)
(V
CC = 2.5 to 4.0 V, VSS = 0 V, Ta = 20 to 85°C, unless otherwise noted.)
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