99
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Note: The RESETOUT output goes “H” in synchronized with the rise of the φ clock that is anywhere between a few cycles and 10-several cycles after RESET
input goes “H”.
Table 46 Timing requirements in memory expansion mode and microprocessor mode
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, in high-speed mode, unless otherwise noted)
ONW input setup time
ONW input hold time
Data bus setup time
Data bus hold time
ONW input setup time
ONW input hold time
Data bus setup time
Data bus hold time
tsu (ONW-φ)
th (φ-ONW)
tsu (DB-φ)
th (φ-DB)
tsu (ONW-RD), tsu (ONW-WR)
th (RD-ONW), th (WR-ONW)
tsu (DB-RD)
th (RD-DB)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min. Typ. Max.
Symbol
Unit
–20
–20
50
0
–20
–20
50
0
Table 47 Switching characteristics in memory expansion mode and microprocessor mode
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, in high-speed mode, unless otherwise noted)
φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width
AD15–AD8 delay time
AD7–AD0 delay time
AD15–AD8 valid time
AD7–AD0 valid time
SYNC delay time
SYNC valid time
Data bus delay time
Data bus valid time
RD pulse width, WR pulse width
RD pulse width, WR pulse width
(When one-wait is valid)
AD15–AD8 delay time
AD7–AD0 delay time
AD15–AD8 valid time
AD7–AD0 valid time
Data bus delay time
Data bus valid time
RESETOUT output delay time
RESETOUT output valid time (Note)
tC(φ)
tWH(φ)
tWL(φ)
td(φ-AH)
td(φ-AL)
tV(φ-AH)
tV(φ-AL)
td(φ-SYNC)
tV(φ-SYNC)
td(φ-DB)
tV(φ-DB)
tWL(RD), tWL(WR)
td(AH-RD), td(AH-WR)
td(AL-RD), td(AL-WR)
tV(RD-AH), tV(WR-AH)
tV(RD-AL), tV(WR-AL)
td(WR-DB)
tV(WR-DB)
td(RESET-RESETOUT)
tV(φ-RESETOUT)
Limits
Parameter
Min. Typ. Max.
Symbol Unit
Test
conditions
Fig. 83
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tC(XIN)–10
tC(XIN)–10
2
2
10
tC(XIN)–10
3tC(XIN)–10
tC(XIN)–35
tC(XIN)–40
2
2
10
0
35
40
30
30
200
100
2tC(XIN)
16
20
5
5
16
5
15
tC(XIN)–16
tC(XIN)–20
5
5
15
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