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PD70F3003A, 70F3025A, 70F3003A(A)

Data Sheet U13189EJ5V1DS

(1) Clock timing

Parameter Symbol Conditions MIN. MAX. Unit

X1 input cycle <1> tCYX Direct mode 15 Note 1 ns

PLL mode 151

Note 2

Note 3 ns

(PLL lock status)

X1 input width, high <2> tWXH Direct mode 6 ns

PLL mode 60 ns

X1 input width, low <3> tWXL Direct mode 6 ns

PLL mode 60 ns

X1 input rise time <4> tXR Direct mode 7 ns

PLL mode 10 ns

X1 input fall time <5> tXF Direct mode 7 ns

PLL mode 10 ns

CPU operating frequency —

Note 4 33 MHz

CLKOUT output cycle <6> tCYK 30 Note 5 ns

CLKOUT width, high <7> tWKH 0.5 T – 5 ns

CLKOUT width, low <8> tWKL 0.5 T – 5 ns

CLKOUT rise time <9> tXR 5 ns

CLKOUT fall time <10> tXF 5 ns

X1 ↓→ CLKOUT delay time <11> tDXK Direct mode 3 17 ns

Notes 1. When A/D converter used: 100 ns

When A/D converter not used: 250 ns

2. When using A/D converter: The value when

= 5 × fXX and

= fXX are set. Setting

= 1/2 × fXX is

prohibited.

When not using A/D converter: The value when

= 5 × fXX,

= fXX, and

= 1/2 × fXX are set.

3. When using A/D converter: 250 ns (when

= 5 × fXX is set) and 200 ns (when

= fXX is set). Setting

= 1/2 × fXX is prohibited.

When not using A/D converter: 250 ns (when

= 5 × fXX,

= fXX, and

= 1/2 × fXX are set).

4. When A/D converter used: 5 MHz

When A/D converter not used: 2 MHz

5. When A/D converter used: 200 ns

When A/D converter not used: 500 ns

Remark T = t

CYK

<1>

<2>

<4>

<11>

<5>

<6>

<7>

<9> <10>

<8>

<3>

X1 (input)

CLKOUT (output)

<11>

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 ... 48 49

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