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PD70F3003A, 70F3025A, 70F3003A(A)

Data Sheet U13189EJ5V1DS

(7) Bus hold timing (1/2)

Parameter Symbol Conditions MIN. MAX. Unit

HLDRQ setup time (to CLKOUT↓) <54> tSHOK 5 ns

HLDRQ hold time (from CLKOUT↓) <55> tHKHQ 5 ns

Delay time from HLDAK to CLKOUT↑

<56> tDKHA 20 ns

HLDRQ high-level width <57> tWHQH T + 10 ns

HLDAK low-level width <58> tWHAL

–40°C ≤ TA ≤ +70°C

T – 10 ns

70°C < TA ≤ 85°C

T – 12 ns

Delay time from CLKOUT↑ to bus float

<59> tDKF 20 ns

Delay time from HLDAK↑ to bus output

<60> tDHAC –3 ns

Delay time from HLDRQ↓ to HLDAK↓

<61> tDHQHA1

(2 n + 7.5) T + 20 ns

Delay time from HLDRQ↑ to HLDAK↑

<62> tDHQHA2 0.5 T 1.5 T + 20 ns

Remarks 1. T = tCYK

2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when

the programmable wait state is inserted.

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