Renesas M32R-FPU Manual do Utilizador descarregar pdf (Página 168)

APPENDICES

APPENDICES-10

M32R-FPU Software Manual (Rev.1.01)

Appendix Figure 3.2.1 Pipeline Flow with no Stall (1)

Appendix 3.2 Pipeline Basic Operation

(1) Pipeline Flow with no Stall

The following diagram shows an ideal pipeline flow that has no stall and executes each

instruction in 1 clock cycle. (Since this is just an ideal case, all instructions may not be

piplined in.)

APPENDIX 3

Appendix 3 Pipeline Processing

<Case 1> Integer instructions (register-to-register) are executed continuously

IF D E WB

IF D WBE

DWBE

IF D WBE

<Case 2> Load/store instructions to destination are accessed in 1 cycle continuously

IF D E WB

ST R0,@-R15

ST R1,@-R15

LDI R0,#1

ADD R0,R1

OR R0,R2

CMP R0,R3

IF D WBMEM2

MEM1 MEM2

E MEM1

IF D E WB

LD R2,@R15+

LD R3,@R15+

IF D WBMEM2

MEM1 MEM2

E MEM1

IF D E WB

LD R0,@R2

LDI R1,#1

IF D WB

MEM1 MEM1 MEM2

IF D E WB

ADD R1,R3

OR R1,R4

IF D WBE

<Case 3> Register-register instructions are executed with no register dependency following

a load/store instruction (out-of-order-completion)

* A multi-cycle instruction, such as multiply or divide, executes

multiple cycles in the E stage.

* A multi-cycle instruction, such as multiply or divide, executes multiple

cycles in the E stage.

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