Renesas MN4 Especificações

Consulte online ou descarregue Especificações para Chaves de fendas elétricas Renesas MN4. Renesas MN4 Specifications Manual do Utilizador

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APPLICATION NOTE
R01AN0924EJ0100 Rev.1.00 Page 1 of 40
Feb 10, 2012
V850E2/MN4
CSIH Control
Introduction
This application note explains how to set up the CSIH (clocked three-wire serial interface) and also gives an outline of
the operation and describes the procedures for using a sample program. The sample program transmits and receives data
between the CSIH0 and CSIH3. The CSIH0 transmits data in master mode, while the CSIH3 receives data in slave
mode. The sample program uses two memory modes: direct access modes and dual buffer mode.
Target Device
V850E2/MN4 Microcontrollers
Contents
1. Overview ........................................................................................................................................... 2
2. Usage Environment........................................................................................................................... 8
3. Software ............................................................................................................................................ 9
4. Sample Application.......................................................................................................................... 10
R01AN0924EJ0100
Rev.1.00
Feb 10, 2012
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Resumo do Conteúdo

Página 1 - V850E2/MN4

APPLICATION NOTE R01AN0924EJ0100 Rev.1.00 Page 1 of 40 Feb 10, 2012 V850E2/MN4 CSIH Control Introduction This application note explains how t

Página 2 - 1. Overview

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 10 of 40 Feb 10, 2012 4. Sample Application This section explains how to set up the CSIH

Página 3

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 11 of 40 Feb 10, 2012 4.1.2 Master Direct-Access Transmit-Only Mode Master direct-acce

Página 4

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 12 of 40 Feb 10, 2012 4.1.3 Slave Direct-Access Receive-Only Mode Slave direct-access

Página 5

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 13 of 40 Feb 10, 2012 4.1.4 Master Dual-Buffer Transmit-Only Mode Master dual-buffer t

Página 6 - 1.3 Interrupt Enabling

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 14 of 40 Feb 10, 2012 4.1.5 Slave Dual-Buffer Receive-Only Mode Slave dual-buffer recei

Página 7 - 1.4 Main Loop Processing

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 15 of 40 Feb 10, 2012 4.1.6 Communication Error Interrupt Processing If a communication

Página 8 - 2.2 Development Environment

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 16 of 40 Feb 10, 2012 4.2 Register Setup This section explains how to set up the relevan

Página 9 - 3.1 File Organization

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 17 of 40 Feb 10, 2012 4.2.2 CSIH Control Register 2 (CSIHnCTL2) The CSIHnCTL2 register

Página 10 - 4.1 Flow Charts

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 18 of 40 Feb 10, 2012 Setting example CSIHnCTL2 = 0x2104; /* master mode;

Página 11

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 19 of 40 Feb 10, 2012 4.2.3 CSIH Control Register 0 (CSIHnCTL0) The CSIHnCTL0 register

Página 12

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 2 of 40 Feb 10, 2012 1. Overview This application note explains the following four opera

Página 13

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 20 of 40 Feb 10, 2012 Figure 4.9 CSIHnCTL0 Register Format (2/2) CSIHnCTL0 = 0x00;

Página 14

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 21 of 40 Feb 10, 2012 4.2.4 CSIH Control Register 1 (CSIHnCTL1) The CSIHnCTL1 register

Página 15

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 22 of 40 Feb 10, 2012 Figure 4.11 CSIHnCTL1 Register Format (2/3)

Página 16 - 4.2 Register Setup

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 23 of 40 Feb 10, 2012 Figure 4.12 CSIHnCTL1 Register Format (3/3) CSIHnCTL1 = 0x00010

Página 17

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 24 of 40 Feb 10, 2012 4.2.5 CSIH Configuration Register x (CSIHnCFGx) The CSIHnCFGx reg

Página 18

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 25 of 40 Feb 10, 2012 Figure 4.14 CSIHnCFGx Register Format (2/5)

Página 19

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 26 of 40 Feb 10, 2012 Figure 4.15 CSIHnCFGx Register Format (3/5)

Página 20

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 27 of 40 Feb 10, 2012 Figure 4.16 CSIHnCFGx Register Format (4/5)

Página 21

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 28 of 40 Feb 10, 2012 Figure 4.17 CSIHnCFGx Register Format (5/5) CSIHnCFG0 = 0x0800

Página 22

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 29 of 40 Feb 10, 2012 4.2.6 CSIH Memory Control Register 0 (CSIHnMCTL0) The CSIHnMCTL0

Página 23

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 3 of 40 Feb 10, 2012 The main points in slave dual-buffer receive-only mode are illustra

Página 24

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 30 of 40 Feb 10, 2012 4.2.7 CSIH Status Clear Register 0 (CSIHnSTCR0) The CSIH can dete

Página 25

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 31 of 40 Feb 10, 2012 /* Clear status flags to 0 */ CSIHnTMOEC = 1; /* Clear timeout

Página 26

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 32 of 40 Feb 10, 2012 4.3 Memory Modes The CSIH supports FIFO mode, dual buffer mode, tr

Página 27

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 33 of 40 Feb 10, 2012 4.4 Function Specifications This section describes the specifica

Página 28

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 34 of 40 Feb 10, 2012 [Function Name] hbus_initial() [Function] Initializes the AHB

Página 29

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 35 of 40 Feb 10, 2012 [Function Name] display() [Function] Controls the LEDs accordi

Página 30

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 36 of 40 Feb 10, 2012 [Function Name] csih_receive_2_initial() [Function] The CSIH3

Página 31

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 37 of 40 Feb 10, 2012 [Function Name] csih_transmit_2_initial() [Function] The CSIH0

Página 32 - 4.3 Memory Modes

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 38 of 40 Feb 10, 2012 4.4.5 Interrupt Processing (interrupt.c) [Function Name] int_csi

Página 33

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 39 of 40 Feb 10, 2012 [Function Name] int_csih3ire() [Function] Processes CSIH3 macr

Página 34

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 4 of 40 Feb 10, 2012 The main points in master direct-access transmit-only mode (Job mod

Página 35

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 40 of 40 Feb 10, 2012 Website and Support Renesas Electronics Website http://www.renesa

Página 36

A-1 Revision Record Description Rev. Date Page Summary 1.00 Feb 10, 2012 — First edition issued

Página 37

General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed

Página 38

Notice1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to chan

Página 39

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 5 of 40 Feb 10, 2012 The main points in slave direct-access receive-only mode are illust

Página 40 - Website and Support

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 6 of 40 Feb 10, 2012 The basic communication specifications are shown below. Memory mode

Página 41 - Revision Record

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 7 of 40 Feb 10, 2012 1.4 Main Loop Processing • The operation of data transfer via the

Página 42

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 8 of 40 Feb 10, 2012 2. Usage Environment This section provides the circuit diagram and

Página 43 - SALES OFFICES

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 9 of 40 Feb 10, 2012 3. Software This section describes the organization of the compress

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