Renesas MN4 Especificações descarregar pdf (Página 30)

V850E2/MN4 CSIH Control

R01AN0924EJ0100 Rev.1.00 Page 30 of 40

Feb 10, 2012

4.2.7 CSIH Status Clear Register 0 (CSIHnSTCR0)

The CSIH can detect five errors: data consistency error, parity error, overrun error, timeout error, and overflow error.

The parity error, data consistency error, and timeout error can be individually enabled or disabled by the CSIHnSTCR0

In this sample program, when receive error interrupt CSIHTIRE is detected, the relevant error flags are cleared by

setting each bit in the status clear register to 1.

Figure 4.19 CSIHnSTCR0 Register Format

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 42 43

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