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V850E2/MN4 CSIH Control

R01AN0924EJ0100 Rev.1.00 Page 21 of 40

Feb 10, 2012

4.2.4 CSIH Control Register 1 (CSIHnCTL1)

The CSIHnCTL1 register controls the communication. It mainly specifies the interrupt timing and interrupt delay mode

and selects the active output level of each chip select signal and the chip select signal operation to perform after the last

data is transferred.

Figure 4.10 CSIHnCTL1 Register Format (1/3)

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 42 43

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