Rev. 1.0, 07/03, page 22 of 38
The RAS3, CAS and RD/WR signals and specific address signals specify a command for
synchronous DRAM. The synchronous DRAM commands are NOP, auto-refresh (REF), self-
refresh (SELF), precharge all banks (PALL), row address strobe bank active (ACVT), read
(READ), read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode
register setting (MRS).
Byte specification is performed by DQMUU, DQMUL, DQMLU, and DQMLL. A read/write is
performed for the byte for which the corresponding DQM is low. In big-endian mode, DQMUU
specifies an access to address 4n, and DQMLL specifies an access to address 4n + 3. In little-
endian mode, DQMUU specifies an access to address 4n + 3, and DQMLL specifies an access to
address 4n.
2.2.2 Power-On Sequence (SH7727)
To use the synchronous DRAM, specify modes after power-on. To initialize the synchronous
DRAM correctly, first specify the bus state controller registers and then specify the synchronous
DRAM mode register. When specifying the synchronous DRAM mode register, the address
signal value is latched depending on the combination of RAS, CAS, and RD/WR signals. In this
case, the bus state controller functions as follows. To write a designated value X to the DRAM
mode register, write data to address H'FFFFD000 + X for area 2 of synchronous DRAM and write
data to H'FFFFE000 + X for area 3 of synchronous DRAM. At this time, data written at addresses
H'FFFFD000 + X and H'FFFFE000 + X is ignored and the DRAM mode register is written in byte
units.
To specify burst read/single write, CAS latency as 1 to 3, sequential as lap type, and burst length
as 1, write arbitrary data in byte units to the addresses listed below.
Area 2 Area 3
32-bit bus width CAS latency 1 H'FFFFD840 H'FFFFE840
CAS latency 2 H'FFFFD880 H'FFFFE880
CAS latency 3 H'FFFFD8C0 H'FFFFE8C0
Area 2 Area 3
16-bit bus width CAS latency 1 H'FFFFD420 H'FFFFE420
CAS latency 2 H'FFFFD440 H'FFFFE440
CAS latency 3 H'FFFFD460 H'FFFFE460
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