Renesas SH7709S Manual do Utilizador descarregar pdf (Página 36)

Rev. 1.0, 07/03, page 32 of 38

Vdd

VddQ

Vss

VssQ

3.3V

GND

Vdd

VddQ

Vss

VssQ

3.3V

GND

A15

SH7727 128-Mbit SDRAM(×16)

128-Mbit SDRAM(×16)

A14

A13

CKIO

CKE

RD/

DQMUU

DQMUL

D31

D16

D15

BA1

BA0

A11

CLK

CKE

DQMU

DQML

DQ15

DQ0

BA1

BA0

A11

CLK

CKE

DQMU

DQML

DQ15

DQ0

DQMLU

DQMLL

Figure 2.11 Interface between SDRAM (uPD45128163) and SH7727

2.2.7 HM5225165B-B6 (4 Mwords × 16 bits × 4 banks)

Bus State Controller (BSC) Settings: When a SDRAM (HM5225165B-B6) is connected to area

3 of the SH7727 via a 16-bit bus, the bus state controller (BSC) must be specified as summarized

below. Table 2.12 lists the BSC register settings.

Note that the interface between SDRAM and the SH7727 is performed with bus clock = 66 MHz,

CL = 2, TPC = 2, RCD = 2, TRWL = 1, and TRAS = 4.

1 2 ... 31 32 33 34 35 36 37 38 39 40 41 42 43 44

SH-3, SH3-DSP SDRAM Interface 1
Cautions 2
Rev. 1.0, 07/03, page 3
Contents 4
Rev. 1.0, 07/03, page 2 of 38 6
Rev. 1.0, 07/03, page 3 of 38 7
Rev. 1.0, 07/03, page 4 of 38 8
Rev. 1.0, 07/03, page 5 of 38 9
Register Name 10
Rev. 1.0, 07/03, page 7 of 38 11
Rev. 1.0, 07/03, page 9 of 38 13

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