Renesas SH7709S Manual do Utilizador descarregar pdf (Página 9)

Rev. 1.0, 07/03, page 5 of 38

A7 to A5 CAS latency

A4 0 (Burst type = sequential)

A3 to A1 000 (Burst length 1)

Before specifying the mode register, 100 µs of idle time (differs depending on the memory

manufacturer) required for synchronous DRAM must be ensured after power-on. If the pulse

width of the reset signal is longer than this idle time, the mode register can be specified

immediately after power-on. In addition, dummy auto-refresh cycles must be executed for the

number of times specified by the manufacturer (normally 8 times) or more. Dummy auto-refresh

cycles are normally specified to be executed automatically during initializations after auto-refresh

setting. However, to ensure execution of the auto-refresh cycles, the time intervals between refresh

requests must be shortened while the dummy cycles are executed. Note that the auto-refresh cycles

must be executed in order to initialize the synchronous DRAM internal address counter because

the synchronous DRAM internal address counter cannot be initialized by a normal read or write

access.

2.1.3 HM5264165F-B60 (1 Mword × 16 bits × 4 banks)

Bus State Controller (BSC) Settings: When two SDRAMs (HM5264165F-B60) are connected to

area 3 of the SH7709S, SH7729R, or SH7706 via a 16-bit bus, the bus state controller (BSC) must

be specified as summarized below. Table 2.1 lists the BSC register setting.

Note that the interface between the SDRAM and SH7709S, SH7729R or SH7706 is performed

with bus clock = 66 MHz, CL = 2, TPC = 2, RCD = 2, TRWL = 1, and TRAS = 4.

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Renesas SH7709S Manual do Utilizador Página 9