
Rev. 1.0, 07/03, page 36 of 38
Vdd
VddQ
Vss
VssQ
3.3V
GND
Vdd
VddQ
Vss
VssQ
3.3V
GND
A16
SH7727 256-Mbit SDRAM(×16)
256-Mbit SDRAM(×16)
A15
A14
:
:
:
:
A2
CKIO
CKE
RD/
DQMUU
DQMUL
D31
D16
:
:
D15
D0
BA1
BA0
A12
:
:
:
:
A0
CLK
CKE
DQMU
DQML
DQ15
DQ0
BA1
BA0
A12
:
:
:
:
A0
CLK
CKE
DQMU
DQML
DQ15
DQ0
DQMLU
DQMLL
Figure 2.13 Interface between SDRAM (HM5225165B-B6) and SH7727
2.2.9 HM5257165B-A6 (8 Mwords × 16 bits × 4 banks)
Bus State Controller (BSC) Settings: When an SDRAM (HM5257165B-A6) is connected to
area 3 of the SH7727 via a 16-bit bus, the bus state controller (BSC) must be specified as
summarized below. Table 2.14 lists the BSC register settings.
Note that the interface between SDRAM and the SH7727 is performed with bus clock = 66 MHz,
CL = 2, TPC = 2, RCD = 2, TRWL = 1, and TRAS = 4.
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