Renesas PROM Programming Adapter PCA7408 Manual do Utilizador descarregar pdf (Página 32)

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP

Rev.1.00 Oct 01, 2002 page 32 of 110

REJ03B0134-0100Z

8.6.1 I

C Data Shift Register

The I

C data shift register (S0 : address 00D716) is an 8-bit shift

When transmit data is written into this register, it is transferred to the

outside from bit 7 in synchronization with the SCL clock, and each

time one-bit data is output, the data of this register are shifted one bit

to the left. When data is received, it is input to this register from bit 0

in synchronization with the SCL clock, and each time one-bit data is

input, the data of this register are shifted one bit to the left.

The I

C data shift register is in a write enable status only when the

ESO bit of the I

C control register (address 00DA16) is “1.” The bit

counter is reset by a write instruction to the I

C data shift register.

When both the ESO bit and the MST bit of the I

C status register

(address 00D916) are “1,” the SCL is output by a write instruction to

the I

C data shift register. Reading data from the I

C data shift regis-

ter is always enabled regardless of the ESO bit value.

Note: To write data into the I

C data shift register after setting the MST bit to

“0” (slave mode), keep an interval of 8 machine cycles or more.

Fig. 8.6.2 Data Shift Register

C data shift register (S0) [Address 00D7

]

ata

Shif

ster

Thi

s an 8-

t s

hif

t reg

ster to store

receive data and write transmit data.

eterm

nate

ote:

“

”

(

)

ame

0 to

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 111 112

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