39
3851 Group
(Built-in 16 KB ROM)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 48 State transitions of system clock
C
M
7
=
0
C
M
6
=
1
C
M
5
=
0
(
8
M
H
z
o
s
c
i
l
l
a
t
i
n
g
)
C
M
4
=
0
(
3
2
k
H
z
s
t
o
p
p
e
d
)
M
i
d
d
l
e
-
s
p
e
e
d
m
o
d
e
(
f
(φ)
=
1
M
H
z
)
C
M
7
=
0
C
M
6
=
1
C
M
5
=
0
(
8
M
H
z
o
s
c
i
l
l
a
t
i
n
g
)
C
M
4
=
1
(
3
2
k
H
z
o
s
c
i
l
l
a
t
i
n
g
)
M
i
d
d
l
e
-
s
p
e
e
d
m
o
d
e
(
f
(φ)
=
1
M
H
z
)
C
M
7
=
0
C
M
6
=
0
C
M
5
=
0
(
8
M
H
z
o
s
c
i
l
l
a
t
i
n
g
)
C
M
4
=
0
(
3
2
k
H
z
s
t
o
p
p
e
d
)
H
i
g
h
-
s
p
e
e
d
m
o
d
e
(
f
(φ)
=
4
M
H
z
)
CM
7
=1
CM
6
=0
CM
5
=0(8 MHz oscillating)
CM
4
=1(32 kHz oscillating)
L
o
w
-
s
p
e
e
d
m
o
d
e
(
f
(φ)
=
1
6
k
H
z
)
C
M
7
=
1
C
M
6
=
0
C
M
5
=
1
(
8
M
H
z
s
t
o
p
p
e
d
)
C
M
4
=
1
(
3
2
k
H
z
o
s
c
i
l
l
a
t
i
n
g
)
Low-speed mode
(f(φ)=16 kHz)
C
M
7
=
0
C
M
6
=
0
C
M
5
=
0
(
8
M
H
z
o
s
c
i
l
l
a
t
i
n
g
)
C
M
4
=
1
(
3
2
k
H
z
o
s
c
i
l
l
a
t
i
n
g
)
H
i
g
h
-
s
p
e
e
d
m
o
d
e
(
f
(φ)
=
4
M
H
z
)
CM
4
: Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : X
CIN-XCOUT oscillating function
CM
5
: Main clock (XIN- XOUT) stop bit
0 : Operating
1 : Stopped
CM
7
, CM
6
: Main clock division ratio selection bits
b7 b6
0 0 : φ = f(X
IN)/2 ( High-speed mode)
0 1 : φ = f(X
IN)/8 (Middle-speed mode)
1 0 : φ = f(X
CIN)/2 (Low-speed mode)
1 1 : Not available
R
e
s
e
C
M
4
“
1
”←
→“
0
”
C
M
4
“
0
”←
→“
1
”
C
M
6
“
1
”←
→“
0
”
C
M
4
“
1
”←
→“
0
”
C
M
6
“
1
”←
→“
0
”
C
M
7
“
1
”←
→“
0
”
C
M
4
“
1
”←
→“
0
”
C
M
5
“
1
”←
→“
0
”
CM
6
“1”←→“0”
C
M
6
“
1
”←
→“
0
”
CPU mode register
b
7b
4
C
M
7
“
0
”←
→“
1
”
C
M
6
“
1
”←
→“
0
”
(CPUM : address 003B
16
)
Notes
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode.
4 : When bit 0 of MISRG is “0” and the stop mode is ended, a delay of approximately 1 ms occurs by connecting timer 1 in middle/high-speed
mode.
5 : When bit 0 of MISRG is “0” and the stop mode is ended, the following is performed.
(1) After the clock is restarted, a delay of approximately 256 ms occurs in low-speed mode if Timer 12 count source selection bit is “0”.
(2) After the clock is restarted, a delay of approximately 16 ms occurs in low-speed mode if Timer 12 count source selection bit is “1”.
6 : Wait until oscillation stabilizes after oscillating the main clock X
IN
before the switching from the low-speed mode to middle/high-speed
mode.
7 : The example assumes that 8 MHz is being applied to the X
IN
pin and 32 kHz to the X
CIN
pin.
φ
indicates the internal clock.
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