
7
3851 Group
(Built-in 16 KB ROM)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 6 Memory map of special function register (SFR)
0
0
2
01
6
0
0
2
11
6
0
0
2
21
6
0
0
2
31
6
002416
0
0
2
51
6
0
0
2
61
6
0
0
2
71
6
0
0
2
81
6
0
0
2
91
6
0
0
2
A1
6
0
0
2
B1
6
0
0
2
C1
6
0
0
2
D1
6
0
0
2
E1
6
0
0
2
F1
6
0
0
3
01
6
003116
0
0
3
21
6
0
0
3
31
6
003416
0
0
3
51
6
003616
003716
0
0
3
81
6
003916
0
0
3
A1
6
0
0
3
B1
6
003C16
0
0
3
D1
6
0
0
3
E1
6
003F16
0
0
0
01
6
0
0
0
11
6
0
0
0
21
6
0
0
0
31
6
000416
0
0
0
51
6
0
0
0
61
6
0
0
0
71
6
0
0
0
81
6
0
0
0
91
6
0
0
0
A1
6
0
0
0
B1
6
0
0
0
C1
6
0
0
0
D1
6
0
0
0
E1
6
0
0
0
F1
6
0
0
1
01
6
001116
0
0
1
21
6
0
0
1
31
6
001416
0
0
1
51
6
001616
001716
0
0
1
81
6
001916
0
0
1
A1
6
0
0
1
B1
6
001C16
0
0
1
D1
6
0
0
1
E1
6
001F16
P
o
r
t
P
0
(
P
0
)
P
o
r
t
P
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
0
D
)
P
o
r
t
P
1
(
P
1
)
P
o
r
t
P
1
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
1
D
)
P
o
r
t
P
2
(
P
2
)
P
o
r
t
P
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
2
D
)
P
o
r
t
P
3
(
P
3
)
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
3
D
)
P
o
r
t
P
4
(
P
4
)
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
4
D
)
Transmit/Receive buffer register (TB/RB)
S
e
r
i
a
l
I
/
O
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
S
I
O
S
T
S
)
S
e
r
i
a
l
I
/
O
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
I
O
C
O
N
)
UART control register (UARTCON)
B
a
u
d
r
a
t
e
g
e
n
e
r
a
t
o
r
(
B
R
G
)
Interrupt control register 2 (ICON2)
A-D conversion low-order register (ADL)
Prescaler Y (PREY)
Timer Y (TY)
A-D control register (ADCON)
A-D conversion high-order register (ADH)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Prescaler 12 (PRE12)
Timer 2 (T2)
Prescaler X (PREX)
Timer X (TX)
Timer 1 (T1)
Timer XY mode register (TM)
I
2
C
data shift register (S0)
I
2
C address register (S0D)
I
2
C status register (S1)
I
2
C control register (S1D)
I
2
C
clock control register (S2)
I
2
C start/stop condition control register (S2D)
MISRG
Watchdog timer control register (WDTCON)
P
W
M
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
W
M
C
O
N
)
P
W
M
p
r
e
s
c
a
l
e
r
(
P
R
E
P
W
M
)
P
W
M
r
e
g
i
s
t
e
r
(
P
W
M
)
Timer count source selection register (TCSS)
Reserved ✽
R
e
s
e
r
v
e
d
✽
Reserved ✽
✽ Reserved : Do not write “1” to this address.
Reserved ✽
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