Renesas PCA4738S-42A Especificações Página 49

  • Descarregar
  • Adicionar aos meus manuais
  • Imprimir
  • Página
    / 55
  • Índice
  • MARCADORES
  • Avaliado. / 5. Com base em avaliações de clientes
Vista de página 48
48
3851 Group
(Built-in 16 KB ROM)
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 19 Switching characteristics 1
(V
CC = 4.0 to 5.5 V, VSS = 0 V, Ta = 20 to 85 °C, unless otherwise noted)
Serial I/O clock output H pulse width
Serial I/O clock output L pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
tWH (SCLK)
tWL (SCLK)
td (SCLK-TXD)
tV (SCLK-TXD)
tr (SCLK)
tf (SCLK)
tr (CMOS)
tf (CMOS)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
tC(SCLK)/230
tC(SCLK)/230
30
Typ.
10
10
Max.
140
30
30
30
30
Symbol Unit
Notes 1: For tWH(SCLK), tWL(SCLK), when the P51/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is 0.
2: The X
OUT pin is excluded.
Table 20 Switching characteristics 2
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = 20 to 85 °C, unless otherwise noted)
Serial I/O clock output H pulse width
Serial I/O clock output L pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
tWH (SCLK)
tWL (SCLK)
td (SCLK-TXD)
tV (SCLK-TXD)
tr (SCLK)
tf (SCLK)
tr (CMOS)
tf (CMOS)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
tC(SCLK)/250
tC(SCLK)/250
30
Typ.
20
20
Max.
350
50
50
50
50
Symbol Unit
Notes 1: For tWH(SCLK), tWL(SCLK), when the P51/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is 0.
2: The X
OUT pin is excluded.
Vista de página 48
1 2 ... 44 45 46 47 48 49 50 51 52 53 54 55

Comentários a estes Manuais

Sem comentários