Renesas PCA4738S-42A Especificações descarregar pdf (Página 52)

51

3851 Group

(Built-in 16 KB ROM)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Symbol

Parameter

Unit

MULTI-MASTER I

2

C-BUS BUS LINE CHARACTERISTICS

Table 21 Multi-master I

2

C-BUS bus line characteristics

Bus free time

Hold time for START condition

Hold time for SCL clock = “0”

Rising time of both SCL and SDA signals

Data hold time

Hold time for SCL clock = “1”

Falling time of both SCL and SDA signals

Data setup time

Setup time for repeated START condition

Setup time for STOP condition

tBUF

tHD;STA

tLOW

tR

tHD;DAT

tHIGH

tF

tSU;DAT

tSU;STA

tSU;STO

Min.

Max.

Min.

Max.

µs

µs

µs

ns

µs

µs

ns

ns

µs

µs

Standard clock mode

High-speed clock mode

Note: Cb = total capacitance of 1 bus line

Fig. 53 Timing diagram of multi-master I

2

C-BUS

4.7

4.0

4.7

0

4.0

250

4.7

4.0

1000

300

1.3

0.6

1.3

20+0.1Cb

0

0.6

20+0.1Cb

100

0.6

0.6

300

0.9

300

t

B

U

F

t

H

D

:

S

T

A

t

H

D

:

D

A

T

t

L

O

W

t

R

t

F

t

H

I

G

H

t

s

u

:

D

A

T

t

su:STA

t

H

D

:

S

T

A

t

s

u

:

S

T

O

S

CL

P

S

S

r

P

S

D

A

S : START condition

Sr: RESTART condition

P : STOP condition

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