Renesas R8C/15 Informações Técnicas descarregar pdf (Página 67)

R8C/14 Group, R8C/15 Group 9. Clock Generation Circuit

Rev.2.10 Jan 19, 2006 Page 53 of 253

REJ09B0164-0210

9.5 Oscillation Stop Detection Function

The oscillation stop detection function is a function to detect the stop of the main clock oscillating circuit.

The oscillation stop detection function can be enabled and disabled by the OCD1 to OCD0 bits in the

OCD register.

Table 9.5 lists the Specification of Oscillation Stop Detection Function.

When the main clock is the CPU clock source and the OCD1 to OCD0 bits are set to “11b” (oscillation

stop detection function enabled), the system is placed in the following state if the main clock stops.

• OCD2 bit in OCD register = 1 (on-chip oscillator clock selected)

• OCD3 bit in OCD register = 1 (main clock stops)

• CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates)

• Oscillation stop detection interrupt request is generated

9.5.1 How to Use Oscillation Stop Detection Function

• The oscillation stop detection interrupt shares the vector with the voltage monitor 2 interrupt and

the watchdog timer interrupt. When using the oscillation stop detection interrupt and watchdog

timer interrupt, the interrupt cause needs to be determined. Table 9.6 lists the Determine Interrupt

Factor of Oscillation Stop Detection, Watchdog Timer and Voltage Monitor 2 Interrupts.

• When the main clock is re-oscillated after oscillation stop, switch the main clock to the clock

source of the CPU clock and peripheral functions by a program.

• Figure 9.9 shows the Procedure of Switching Clock Source From Low-Speed On-Chip Oscillator

to Main Clock.

• To enter wait mode while using the oscillation stop detection function, set the CM02 bit to “0”

(peripheral function clock does not stop in wait mode).

• Since the oscillation stop detection function is a function preparing to stop the main clock by the

external cause, set the OCD1 to OCD0 bits to “00b” (oscillation stop detection function disabled)

when the main clock stops or oscillates in the program, that is stop mode is selected or the CM05

bit is changed.

• This function cannot be used when the main clock frequency is below 2 MHz. Set the OCD1 to

OCD0 bits to “00b” (oscillation stop detection function disabled).

• When using the low-speed on-chip oscillator clock for the CPU clock and clock sources of

peripheral functions after detecting the oscillation stop, set the HRA01 bit in the HRA0 register to

“0” (low-speed on-chip oscillator selected) and the OCD1 to OCD0 bits to “11b” (oscillation stop

detection function enabled).

When using the high-speed on-chip oscillator clock for the CPU clock and clock sources of

peripheral functions after detecting the oscillation stop, set the HRA01 bit to “1” (high-speed on-

chip oscillator selected) and the OCD1 to OCD0 bits to “11b” (oscillation stop detection function

enabled).

Table 9.5 Specification of Oscillation Stop Detection Function

Item Specification

Oscillation Stop Detection Enable Clock

and Frequency Bandwidth

f(XIN) ≥ 2 MHz

Enabled Condition for Oscillation Stop

Detection Function

Set OCD1 to OCD0 bits to “11b” (oscillation stop detection

function enabled)

Operation at Oscillation Stop Detection Oscillation stop detection interrupt is generated

1 2 ... 62 63 64 65 66 67 68 69 70 71 72 ... 278 279

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