Renesas SuperH SH7343 Informações Técnicas descarregar pdf (Página 145)

Target interface (SH7760) Jun. 30, 2009 (Second Edition)

MDR connector

Signals

CPU Pin No.

No.

Signal

Input/

Output

P-LBGA2121-256

No.

Signal

Input/

Output

P-LBGA2121-256

1 AUDCK Output H19/P19 2 GND

3 AUDATA0 Output K19/T19 4 GND

5 AUDATA1 Output K20/T20 6 GND

7 AUDATA2 Output K19/R19 8 GND

9 AUDATA3 Output J20/R20 10 GND

11 AUDSYNC Output H20/P20 12 GND

13 N.C. 14 GND

15 N.C. 16 GND

17 TCK Input C15 18 GND

19 TMS Input C10 20 GND

21 TRST Input D10 22 GND

23 TDI Input D12 24 GND

25 TDO Output C12 26 GND

ASEBRK

/BRKACK

Input/Output C8 28 GND

29 VCC

Output 30 GND

31 RESET Output B1 32 GND

33 GND 34 GND

35 N.C. 36 GND

・ For the pin where stated as N.C. in the table, leave the signal unconnected.

*1: Input/output is based on the target system.

*2: 2 routings of AUD ports are available. Choose either of them.

*3: For VCC, connect I/O power of CPU. Debugging can be performed even if the signal is N.C., however, by connecting I/O power, leak during

the target system power OFF can be prevented.

Target connection reference diagram

MDR connector specifications

Recommended connector

Manufacturer 3M

Model 10236-52A2JL

(Top view on the target board)

(Side view on the target board)

(Pin Configuration)

(For detailed dimensions of the connector,

refer to the documentation by manufacturer of the connector.)

*Please look at the pin configuration diagram above and make

sure that the connector is in the right direction before connecting.

Please check the pin number in the signal table above and make sure

the signal and the pin numbers match.

*1:

RESET, which is connected to Pin No. 31 of the connector for debugger, is the signal that debugger uses for monitoring the state of RESET

pin of CPU.

1 2 ... 140 141 142 143 144 145 146 147 148 149 150 ... 203 204

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