Renesas SuperH SH7343 Informações Técnicas descarregar pdf (Página 188)

PALMiCE3 HUDI140 model Hardware Manual Chapter 3 Target Interface Specifications 11

3.2.4 Specifications of H-UDI interface signals

VIL Target voltage ÷ 2 – 0.35

Input voltage level

VIH Target voltage ÷ 2 + 0.35

VOL Under 0.2V

Output voltage level

VOH

Follows the target voltage

(Note, for 5V-spec CPUs, output level will be min. 4.2V - max. 4.7V.)

3.2.5 RSTOUT signal

■ When using PALMiCE3 SuperH

/RSTOUT signal is a signal for requesting reset from PALMiCE3 to the target system. The signal will be output

by open-collector circuit if from PALMiCE3.

Connect this signal to the reset circuit of the whole target system inclusive of CPU and peripherals. It is required

for synchronization at CSIDE startup.

If connection can not be established, you can still press reset switch button on the target system or use

power-on-reset.

3.2.6 The target interface on PALMiCE3 side

The target interface on PALMiCE3 side is described.

No. Signal Remarks No. Signal Remarks

TCK 33Ω Series

GND

TRST

33Ω Series

GND（

ASEMD）

TDO 33Ω Series 10KΩ Pull-up

GND

ASEBRKAK 100Ω Series 10KΩ Pull-up

VCC

TMS 33Ω Series

GND

TDI 33Ω Series

GND

RESET 100Ω Series 100KΩ Pull-down

GND

*1: Potential has been pulled up to the same level as target VCC reference voltage.

Each name of the signal varies depending on the CPU you use.

Besides this manual, also, consult "Technical Information on PALMiCE3" up on our website

(http://www.computex.co.jp/eg/)

Not

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