Renesas SH7641 Informações Técnicas Página 220

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Cache Operation during User Program Break
When cache is enabled, the emulator accesses the memory by the following methods:
At memory write: Writes through the cache, then writes to the memory.
At memory read: Does not change the cache write mode that has been set.
Therefore, when memory read or write is performed during user program break, the cache state
will be changed.
UBC
When [User] is specified in the [UBC mode] list box in the [Configuration] dialog box, the UBC
can be used in the user program.
Do not use the UBC in the user program as it is used by the E10A emulator when [EML] is
specified in the [UBC mode] list box in the [Configuration] dialog box.
Loading Sessions
Information in [JTAG clock] of the [Configuration] dialog box cannot be recovered by loading
sessions. Thus the TCK value will be as follows:
When HS7641KCI01H or HS7641KCI02H is used: TCK = 4.125 MHz
When HS7641KCM01H or HS7641KCM02H is used: TCK = 3.75 MHz
Ports C and J
The AUD and H-UDI pins are multiplexed as shown below.
Table 6.3 Multiplex Functions
Port Function 1 Function 2
C PTC13 (input/output)
*1
/ASEBRKAK (H-UDI)
J PTJ12 (input/output)
*2
AUDSYNC (AUD)
J PTJ11 (input/output)
*2
AUDATA3 (AUD)
J PTJ10 (input/output)
*2
AUDATA2 (AUD)
J PTJ9 (input/output)
*2
AUDATA1 (AUD)
J PTJ8 (input/output)
*2
AUDATA0 (AUD)
Notes: 1. When the emulator is used, PTC13 is not available.
2. When using the AUD function, function 2 must be enabled with the pin function
controller.
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