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Table 6.12 Measurement Item (cont)

Selected Name Option

URAM access stall US (Devices incorporating the U memory can

only be measured.)

Instruction/data access stall cycle MA

Other access cycles than instruction/data NMA

Non-cacheable area access cycle NCC

Non-cacheable area instruction access cycle NCI

Non-cacheable area data access cycle NCD

Cacheable area access cycle CC

Cacheable area instruction access cycle CIC

Cacheable area data access cycle CDC

Access counts other than instruction/data NAM

Non-cacheable area access counts NCN

Non-cacheable area instruction access counts NCIN

Non-cacheable area data access counts NCDN

Cacheable area access counts CN

Cacheable area instruction access counts CIN

Cacheable area data access counts CDN

Each measurement condition is also counted when conditions in table 6.13 are generated.

Table 6.13 Performance Measurement Conditions to be Counted

Measurement Condition Notes

Cache-on counting Accessing the non-cacheable area is counted less than the actual

number of counts. Accessing the cacheable, U memory, and X/Y

memory areas are counted more than the actual number of counts.

Branch count The counter value is incremented by 2. This means that two cycles

are valid for one branch.

Notes: 1. In the non realtime trace mode of the AUD trace, normal counting cannot be

performed because the generation state of the stall or the execution cycle is changed.

2. Since the clock source of the counter is the CPU clock, counting also stops when the

clock halts in the sleep mode.

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