Renesas R8C/Tiny Series Manual descarregar pdf (Página 106)

R8C/10 Group 13.1 Clock Synchronous Serial I/O Mode

Rev.1.20 Jan 27, 2006 page 96 of 180

REJ09B0019-0120

Figure 13.6 Transmit and Receive Operation

• Example of transmit timing (when internal clock is selected)

Stopped pulsing because the TE bit = 0

Write data to U0TB register

Tc = T

CLK

= 2(n + 1) / fi

fi: frequency of U0BRG count source (f

1SIO

, f

8SIO

, f

32SIO

)

n: value set to U0BRG register

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

Transferred from U0TB register to UART0 transmit register

The above timing diagram applies to the case where the register bits are set as follows:

• U0MR register CKDIR bit = 0 (internal clock)

• U0C0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)

• U0IRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty):

Set to “0” when interrupt request is accepted, or set by a program

Transfer clock

U0C1 register

TE bit

U0C1 register

TI bit

CLK

TxD

U0C0 register

TXEPT bit

S0TIC register

IR bit

CLK

Write dummy data to U0TB register

Transferred from U0TB register to UART0 transmit register

fEXT: frequency of external clock

U0C1 register

TE bit

CLK

RxD0

U0C1 register

RI bit

“0”

“1”

“0”

“1”

U0C1 register

RE bit

“0”

“1”

S0RIC register

IR bit

“0”

“1”

Make sure the following conditions are met when input to the CLK0 pin before receiving data is high:

• U0C1 register TE bit = 1 (transmit enabled)

• U0C1 register RE bit = 1 (receive enabled)

• Write dummy data to the U0TB register

Receive data is taken in

Read out from U0RB register

Transferred from UART0 receive register

to U0RB register

Set to “0” when interrupt request is accepted, or set by a program

The above timing diagram applies to the case where the register bits are set as follows:

• U0MR register CKDIR bit = 1 (external clock)

• U0C0 register CKPOL bit = 0 (transmit data output at the falling edge and receive

data taken in at the rising edge of the transfer clock)

1 / fEXT

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5

“0”

“1”

U0C1 register

TI bit

• Example of receive timing (when external clock is selected)

1 2 ... 101 102 103 104 105 106 107 108 109 110 111 ... 198 199

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