R8C/10 Group
Rev.1.20 Jan 27, 2006 page 39 of 180
REJ09B0019-0120
Figure 10.3 Interrupt Control Registers
S
y
m
b
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A
d
d
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s
sA
f
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I
N
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0
I
C
0
0
5
D
1
6
X
X
0
0
X
0
0
0
2
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b
7b6b
5b
4b3b
2b
1b
0
ILVL0
IR
P
O
L
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
(3, 4)
Reserved bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Set to “0”
I
L
V
L
1
ILVL2
N
O
T
E
S
:
1
.
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"
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(2
)
b
7b
6b
5b
4b
3b
2b
1b
0
Bit name FunctionBit symbol
R
W
Symbol Address After reset
KUPIC 004D
16 XXXXX000
2
ADIC 004E16 XXXXX000
2
S0TIC, S1TIC 005116, 005316 XXXXX000
2
S0RIC, S1RIC 005216, 005416 XXXXX000
2
INT2IC 005516 XXXXX000
2
TXIC 005616 XXXXX000
2
TYIC 005716 XXXXX000
2
TZIC 005816 XXXXX000
2
INT1IC 005916 XXXXX000
2
INT3IC 005A16 XXXXX000
2
TCIC 005B16 XXXXX000
2
I
L
V
L
0
IR
I
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t
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r
r
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p
t
p
r
i
o
r
i
t
y
l
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v
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s
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c
t
b
i
t
Interrupt request bit
0
:
I
n
t
e
r
r
u
p
t
n
o
t
r
e
q
u
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s
t
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d
1
:
I
n
t
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r
r
u
p
t
r
e
q
u
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s
t
e
d
ILVL1
ILVL2
Nothing is assigned.
When write, set to “0”. When read, its content is indeterminate.
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b
2b
1b
0
0
0
0
:
L
e
v
e
l
0
(
i
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r
r
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p
t
d
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a
b
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)
0
0
1
:
L
e
v
e
l
1
0
1
0
:
L
e
v
e
l
2
0
1
1
:
L
e
v
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l
3
1
0
0
:
L
e
v
e
l
4
1
0
1
:
L
e
v
e
l
5
1
1
0
:
L
e
v
e
l
6
1
1
1
:
L
e
v
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l
7
b2 b1 b0
0
R
W
R
W
R
W
R
W
(1
)
(b7-b4)
R
W
R
W
R
W
R
W
RW
RW
(1)
R
W
(b7-b6)
N
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d
.
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w
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,
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o
“
0
”
.
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.
(
b
5
)
10.1 Interrupt Overview
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