R8C/10 Group
Rev.1.20 Jan 27, 2006 page 49 of 180
REJ09B0019-0120
Figure 10.14 TCC0 Register and TCC1 Register
______
10.2.4 INT3 Interrupt
_____ ______
INT3 interrupts are triggered by INT3 inputs. The TCC07 bit in the TCC0 register should be se to “0”
______ _______
(INT3). The INT3 input has a digital filter which can be sampled by one of three sampling clocks. The
sampling clock is selected using the TCC11 to TCC10 bits in the TCC1 register. The IR bit in the
INT3IC register is set to “1” (interrupt requested) when the sampled input level matches three times.
The P3_3 bit in the P3 register indicates the previous value before filtering regardless of values set in
the TCC11 to TCC10 bits.
_______
The INT3 pin is shared with the TCIN pin.
_____
When setting the TCC07 bit to “1” (fRING128), INT3 interrupts are triggered by fRING128 clock. The IR
bit in the INT3IC register is set to “1” (interrupt requested) every fRING128 clock cycle or every half
fRING128 clock cycle.
Figure 10.14 shows the TCC0 and TCC1 registers.
10.2 INT Interrupt
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