Renesas R8C/Tiny Series Manual descarregar pdf (Página 111)

R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode

Rev.1.20 Jan 27, 2006 page 101 of 180

REJ09B0019-0120

TxDi

Transfer clock

UiC1 register

TE bit

UiC1 register

TI bit

UiC0 register

TXEPT bit

SiTIC register

IR bit

Tc = 16 (n + 1) / fj or 16 (n + 1) / f

EXT

fj: frequency of UiBRG count source (f

1SIO

, f

8SIO

, f

32SIO

)

EXT

: frequency of UiBRG count source (external clock)

n: value set to UiBRG

i: 0, 1

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

The above timing diagram applies to the case where the register bits

are set as follows:

• UiMR register PRYE bit = 1 (parity enabled)

• UiMR register STPS bit = 0 (1 stop bit)

• UiIRS bit = 1 (an interrupt request occurs when transmit completed):

Set to “0” when interrupt request is accepted, or set by a program

PSP

Start

bit

Parity

bit

Stop

bit

Stopped pulsing

because the TE bit

= “0”

Write data to UiTB register

Transferred from UiTB register to UARTi transmit register

• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)

• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)

Figure 13.9 Transmit Operation

TxDi

Transfer clock

UiC1 register

TE bit

UiC1 register

TI bit

UiC0 register

TXEPT bit

SiRIC register

IR bit

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

The above timing diagram applies to the case where the register

bits are set as follows:

• UiMR register PRYE bit = 0 (parity disabled)

• UiMR register STPS bit = 1 (2 stop bits)

• UiIRS bit = 0 (an interrupt request occurs when transmit buffer

becomes empty)

ST D

SPSPSPSP

Write data to UiTB register

Transferred from UiTB register to UARTi

transmit register

Set to “0” when interrupt request is accepted, or set by a program

Stop

bit

Stop

bit

Start

bit

Tc = 16 (n + 1) / fj or 16 (n + 1) / f

EXT

fj: frequency of UiBRG count source (f

1SIO

, f

8SIO

, f

32SIO

)

EXT

: frequency of UiBRG count source (external clock)

n: value set to UiBRG

i: 0, 1

1 2 ... 106 107 108 109 110 111 112 113 114 115 116 ... 198 199

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