Renesas R8C/Tiny Series Manual descarregar pdf (Página 25)

R8C/10 Group 5. Reset

Rev.1.20 Jan 27, 2006 page 15 of 180

REJ09B0019-0120

Figure 5.2 Reset Sequence

Figure 5.1 CPU Register Status After Reset

b15

Data register(R0)

Address register(A0)

Frame base register(FB)

Program counter(PC)

Interrupt table register(INTB)

User stack pointer(USP)

Interrupt stack pointer(ISP)

Static base register(SB)

Flag register(FLG)

0000

000016

CDZSBOIU

IPL

000016

b19

Content of addresses 0FFFE16 to 0FFFC16

b15

b7 b8

0000016

Data register(R1)

Data register(R2)

Data register(R3)

Address register(A1)

0000

000016

(

)

Content of reset vector

0FFFD

More than 20 cycles are needed

CPU clock

CPU clock ✕ 28cycles

Internal on-chip

oscillation

Flash memory activated time

(CPU clock ✕ 64 cycles)

(1)

1 2 ... 20 21 22 23 24 25 26 27 28 29 30 ... 198 199

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