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Rev.2.10 Apr 14, 2006 page 76 of 378
REJ09B0124-0210
M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit
Figure 8.13 State Transition in Normal Operating Mode
CPU clock
: f(PLL)
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 0
PLL operating mode
PLL operating mode
PLC07 = 0
CM11 = 0
PLC07 = 1
CM11 = 1
(6)
CM04 = 1CM04 = 1 CM04 = 0 CM04 = 0
CM04 = 1
CM04 = 0
CM04 = 1
CM04 = 0
CM07 =1
(3)
CM07 = 0
(2) (4)
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
On-chip oscillator
mode
CM21 = 1
CM21 = 0
(7)
High-speed mode
CPU clock
: f(XIN)
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 0
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
On-chip oscillator
low power dissipation mode
On-chip oscillator
mode
On-chip oscillator
low power dissipation mode
On-chip oscillator
clock oscillation
Main clock oscillation
CM05 = 1
(1)
CM05 = 0
CM04, CM05, CM06, CM07: Bits in CM0 register
CM11, CM15, CM16, CM17: Bits in CM1 register
CM20, CM21 : Bits in CM2 register
PLC07 : Bit in PLC0 register
NOTES:
1. Avoid making a transition when the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting.
2. Wait the main clock oscillation stabilizes.
3. Switch clock after oscillation of sub clock is sufficiently stable.
4. Change bits CM17 and CM16 before changing the CM06 bit.
5. Transit in accordance with arrow.
6. The PM20 bit in the PM2 register become effective when the PLC07 bit is set to 1 (PLL on). Change the PM20 bit when the PLC07 bit is set
to 0 (PLL off). Set the PM20 bit to 0 (2 waits) when PLL clock > 16 MHz.
7. Set the CM06 bit to 1 (divide-by-8 mode) before changing back the operating mode from on-chip oscillator mode to high-speed or middle-speed
mode.
8. When the CM21 bit = 0 (on-chip oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to 1 (divide-by-8 mode)
and the CM15 bit is fixed to 1 (drive capability High).
Medium-speed mode
(divide-by-2)
CPU clock
: f(XIN)/2
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 1
Medium-speed mode
(divide-by-4)
CPU clock
: f(XIN)/4
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 0
Medium-speed mode
(divide-by-8)
CPU clock
: f(XIN)/8
CM07 = 0
CM06 = 1
Medium-speed mode
(divide-by-16)
CPU clock
: f(XIN)/16
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 1
CPU clock
: f(PLL)
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 0
PLC07 = 0
CM11 = 0
PLC07 = 1
CM11 = 1
(6)
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM21 = 1
CM21 = 0
(7)
CM21 = 1
CM21 = 0
High-speed mode
CPU clock
: f(XIN)
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 0
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
Sub clock oscillation
CM05 = 1
(1)
CM05 = 0
Medium-speed mode
(divide-by-2)
CPU clock
: f(XIN)/2
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 1
Medium-speed mode
(divide-by-4)
CPU clock
: f(XIN)/4
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 0
Medium-speed mode
(divide-by-8)
CPU clock
: f(XIN)/8
CM07 = 0
CM06 = 1
Medium-speed mode
(divide-by-16)
CPU clock
: f(XIN)/16
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 1
CPU clock: f(XCIN)
CM07 = 0
CPU clock: f(XCIN)
CM07 = 0
Low-speed modeLow-speed mode
CM05 = 1
(1) (8)
CM05 = 0
CPU clock: f(XCIN)
CM07 = 0
CM06 = 1
CM15 = 1
Low power dissipation mode
- To our customers 1
- Hardware Manual 3
- RENESAS MCU 3
- M16C FAMILY / M16C/60 SERIES 3
- Blank page 6
- How to Use This Manual 7
- 3. Register Notation 9
- Table of Contents 11
- __________ 12
- SFR Page Reference 17
- 1. Overview 25
- 1.2 Performance Overview 26
- 1.3 Block Diagram 28
- 1.4 Product Information 29
- 1.5 Pin Assignments 30
- M16C/6N Group 33
- (M16C/6NM) 33
- 1.6 Pin Functions 37
- 3. Memory 42
- 5. Resets 59
- 5.2 Software Reset 61
- 5.3 Watchdog Timer Reset 61
- 5.5 Internal Space 61
- 6. Processor Mode 62
- 6.2 Setting Processor Modes 63
- Processor Mode Register 0 64
- Processor Mode Register 1 65
- 7.1 Bus Mode 69
- 7.1.1 Separate Bus 69
- 7.1.2 Multiplexed Bus 69
- 7.2 Bus Control 70
- 7.2.2 Data Bus 70
- 7.2.3 Chip Select Signal 70
- 7.2.1 Address Bus 70
- 7.2.4 Read and Write Signals 72
- 7.2.5 ALE Signal 72
- 7.2.6 RDY Signal 73
- HOLD > DMAC > CPU 74
- 7.2.10 Software Wait 76
- 8. Clock Generation Circuit 80
- Figure 8.2 CM0 Register 82
- Figure 8.3 CM1 Register 83
- Figure 8.4 CM2 Register 84
- Figure 8.5 PCLKR Register 85
- CAN0/1 Clock Select Register 86
- PLL Control Register 0 87
- 8.1.1 Main Clock 88
- 8.1.2 Sub Clock 89
- 8.1.4 PLL Clock 90
- 8.2.1 CPU Clock and BCLK 92
- 8.3 Clock Output Function 92
- 8.4 Power Control 93
- 8.4.1 Normal Operating Mode 93
- 8.4.2 Wait Mode 95
- 8.4.3 Stop Mode 97
- REJ09B0124-0210 100
- State after Transition 101
- Current State 101
- 9. Protection 104
- 10.1 Type of Interrupts 105
- 10.2 Software Interrupts 106
- 10.2.2 Overflow Interrupt 106
- 10.2.3 BRK Interrupt 106
- 10.3 Hardware Interrupts 107
- 10.3.1 Special Interrupts 107
- 10.4.1 Fixed Vector Tables 108
- ________ 109
- 10.5 Interrupt Control 110
- Interrupt Control Register 111
- 10.5.1 I Flag 112
- 10.5.2 IR Bit 112
- 10.5.4 Interrupt Sequence 113
- _________ 114
- 10.5.7 Saving Registers 115
- 10.5.9 Interrupt Priority 116
- 10.6 INT Interrupt 118
- Figure 10.11 IFSR0 Register 119
- Figure 10.12 IFSR1 Register 120
- Figure 10.13 IFSR2 Register 121
- 10.7 NMI Interrupt 122
- 10.8 Key Input Interrupt 122
- 10.9 CAN0/1 Wake-up Interrupt 122
- 10.10 Address Match Interrupt 123
- 11. Watchdog Timer 125
- 12. DMAC 127
- ________ ________ 128
- Figure 12.2 DM0SL Register 129
- 12.1 Transfer Cycle 132
- 12.1.4 Effect of RDY Signal 132
- 12.2 DMA Transfer Cycles 134
- 12.3 DMA Enable 135
- 12.4 DMA Request 135
- 13. Timers 137
- 13.1 Timer A 139
- Up/Down Flag 141
- Count Start Flag 141
- One-Shot Start Flag 142
- Trigger Select Register 142
- Clock Prescaler Reset Flag 142
- 13.1.1 Timer Mode 143
- 13.1.2 Event Counter Mode 144
- 13.1.3 One-shot Timer Mode 149
- 13.2 Timer B 154
- 13.2.1 Timer Mode 157
- 13.2.2 Event Counter Mode 158
- Figure 13.20 160
- Figure 14.2 INVC0 Register 164
- Figure 14.3 INVC1 Register 165
- Dead Time Timer 166
- Timer B2 Register 167
- (1) (2) (3) 168
- Timer B2 Mode Register 170
- 15. Serial Interface 173
- _______ _______ 183
- _________ _________ 183
- Setting in UART Mode 191
- 15.1.3 Special Mode 1 (I 199
- Figure 15.23 I 200
- C Mode Block Diagram 200
- _______ ________ 201
- _______ ________ _______ 201
- Function 202
- 15.1.4 Special Mode 2 208
- Undefined 212
- (NOTE 2) 214
- (1) Transmit timing 217
- (2) Receive timing 217
- SIM card 218
- (1) Direct format 219
- (2) Inverse format 219
- 15.2 SI/Oi (i = 3 to 6) 220
- Bit Symbol 222
- 15.2.1 SI/Oi Operation Timing 224
- 15.2.2 CLK Polarity Selection 224
- 16. A/D Converter 226
- A/D Control Register 0 228
- A/D Control Register 1 228
- A/D Control Register 2 229
- A/D Register i (i = 0 to 7) 229
- 16.1 Mode Description 230
- 16.1.1 One-shot Mode 230
- 16.1.2 Repeat Mode 232
- 16.1.3 Single Sweep Mode 234
- 16.1.4 Repeat Sweep Mode 0 236
- 16.1.5 Repeat Sweep Mode 1 238
- 16.2 Function 240
- 16.2.2 Sample and Hold 240
- Data bus low-order 243
- D/A Control Register 244
- D/A Register i (i = 0, 1) 244
- 18. CRC Calculation 245
- Figure 18.3 CRC Calculation 246
- 19. CAN Module 247
- 19.1.3 CAN SFR Registers 248
- 19.4 CAN SFR Registers 252
- 19.5 Operational Modes 258
- Module idle 259
- Module transmits 259
- Module receives 259
- 19.5.5 Bus Off State 260
- CCLKR register 261
- CAN module 261
- 19.8 Bit-rate 262
- 19.11 Basic CAN Mode 265
- 19.14 Listen-Only Mode 266
- 19.15.1 Reception 268
- 19.15.2 Transmission 269
- 19.16 CAN Interrupt 270
- 20. Programmable I/O Ports 271
- 20.4 PCR Register 272
- Figure 20.1 I/O Ports (1) 273
- Figure 20.2 I/O Ports (2) 274
- Figure 20.3 I/O Ports (3) 275
- (inside dotted-line 276
- included) 276
- not included) 276
- Figure 20.5 I/O Ports (5) 277
- Figure 20.6 I/O Pins 277
- Port P8 Direction Register 278
- Port P8 Register 279
- Pull-up Control Register 0 280
- Pull-up Control Register 1 280
- Pull-up Control Register 2 280
- Port Control Register 281
- 21. Flash Memory Version 284
- 21.1 Memory Map 285
- 21.1.1 Boot Mode 286
- 21.2.2 ID Code Check Function 286
- Figure 21.2 ROMCP Register 287
- 21.3 CPU Rewrite Mode 288
- 21.3.1 EW0 Mode 289
- 21.3.2 EW1 Mode 289
- Power Dissipation Mode 294
- 21.3.5 Software Commands 297
- 21.3.6 Data Protect Function 302
- 21.3.8 Full Status Check 304
- 21.4 Standard Serial I/O Mode 306
- 21.4.1 ID Code Check Function 306
- Pin Name I/O 307
- Description 307
- M16C/6N Group (M16C/6NK) 308
- (Flash memory version) 308
- M16C/6N Group (M16C/6NM) 309
- 21.5 Parallel I/O Mode 311
- 21.6 CAN I/O Mode 312
- 21.6.1 ID Code Check Function 312
- _____________ 316
- (ripple) 318
- P-P(ripple) 318
- VCC = 5V 319
- Gain error 321
- Interrupt for 322
- (a) Stop mode release 322
- or 322
- (b) Wait mode release 322
- VCC = 5 V 323
- VCC = 3.3 V 337
- 23. Usage Notes 362
- 23.3 External Clock 364
- 23.5 Power Control 366
- A/D converter 367
- D/A converter 367
- 23.7 Protection 369
- 23.8 Interrupts 370
- 23.8.1 Reading Address 00000h 370
- 23.8.2 Setting SP 370
- 23.8.3 NMI Interrupt 370
- 23.8.5 INT Interrupt 371
- 23.9 DMAC 373
- 23.10 Timers 374
- 23.10.1 Timer A 374
- 23.10.2 Timer B 378
- 23.12 Serial Interface 381
- 23.12.2 Special Modes 382
- 23.12.3 SI/Oi (i = 3 to 6) 383
- 23.13 A/D Converter 384
- 23.14 CAN Module 386
- 23.15 Programmable I/O Ports 391
- 23.16 Dedicated Input Pin 392
- Version MCUs 393
- 23.19.10 Interrupts 396
- 23.19.11 How to Access 396
- 23.19.13 DMA Transfer 396
- 23.21 Noise 398
- Register Index 401
- REVISION HISTORY 403
- Rev.2.10 Apr 14, 2006 411
- Renesas Technology Corp 411
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