Renesas M16C/6NK Informações Técnicas descarregar pdf (Página 208)

Rev.2.10 Apr 14, 2006 page 184 of 378

REJ09B0124-0210

M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface

15.1.4 Special Mode 2

Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are

selectable. Table 15.14 lists the Special Mode 2 Specifications. Figure 15.27 shows the Serial Bus

Communication Control Example (UART2). Table 15.15 lists the Registers to be Used an Settings in

Special Mode 2.

Table 15.14 Special Mode 2 Specifications

Item Specification

Transfer data format Transfer data length: 8 bits

Transfer clock • Master mode

The CKDIR bit in the UiMR register = 0 (internal clock) : fj/(2(n+1))

fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh

• Slave mode

The CKDIR bit = 1 (external clock selected) : Input from CLKi pin

Transmit/receive control Controlled by input/output ports

Transmit start condition Before transmission can start, meet the following requirements

(1)

• The TE bit in the UiC1 register = 1 (transmission enabled)

• The TI bit in the UiC1 register = 0 (data present in the UiTB register)

Receive start condition Before reception can start, meet the following requirements

(1)

• The RE bit in the UiC1 register = 1 (reception enabled)

• The TE bit in the UiC1 register = 1 (transmission enabled)

• The TI bit in the UiC1 register = 0 (data present in the UiTB register)

Interrupt request For transmission, one of the following conditions can be selected

generation timing • The UiIRS bit

(2)

= 0 (transmit buffer empty): when transferring data from the UiTB

• The UiIRS bit =1 (transmission completed): when the serial interface finished

transmitting data from the UARTi transmit register

For reception

• When transferring data from the UARTi receive register to the UiRB register (at

completion of reception)

Error detection Overrun error

(3)

This error occurs if the serial interface started receiving the next data before reading

the UiRB register and received the 7th bit of the next data

Select function Clock phase setting

Selectable from four combinations of transfer clock polarities and phases

i = 0 to 2

NOTES:

1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0

the transfer clock), the external clock is in the high state; if the CKPOL bit = 1 (transmit data output at

the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock

is in the low state.

2. Bits U0IRS and U1IRS are bits 0 and 1 in the UCON register ; the U2IRS bit is bit 4 in the U2C1 register.

3. If an overrun error occurs, the value of UiRB register will be undefined. The IR bit in SiRIC register

remains unchanged.

1 2 ... 203 204 205 206 207 208 209 210 211 212 213 ... 411 412

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