Renesas M16C/6NK Informações Técnicas descarregar pdf (Página 144)

Rev.2.10 Apr 14, 2006 page 120 of 378

REJ09B0124-0210

M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers

Item Specification

Count source • External signals input to TAiIN pin (effective edge can be selected in program)

• Timer B2 overflows or underflows,

Timer Aj overflows or underflows,

Timer Ak overflows or underflows

Count operation • Up-count or down-count can be selected by external signal or program

• When the timer overflows or underflows, it reloads the reload register

contents and continues counting. When operating in free-running mode,

the timer continues counting without reloading.

Divided ratio 1/ (FFFFh - n + 1) for up-count

1/ (n + 1) for down-count n : set value of the TAi register 0000h to FFFFh

Count start condition Set the TAiS bit in the TABSR register to 1 (count starts)

Count stop condition Set the TAiS bit to 0 (count stops)

Interrupt request generation timing

Timer overflow or underflow

TAiIN pin function I/O port or count source input

TAiOUT pin function I/O port, pulse output, or up/down-count select input

Read from timer Count value can be read by reading the TAi register

Write to timer • When not counting and until the 1st count source is input after counting start

Value written to the TAi register is written to both reload register and counter

• When counting (after 1st count source input)

Value written to the TAi register is written to only reload register

(Transferred to counter when reloaded next)

Select function • Free-run count function

Even when the timer overflows or underflows, the reload register content

is not reloaded to it

• Pulse output function

Whenever the timer underflows or underflows, the output polarity of

TAiOUT pin is inverted.

When TAiS bit is set to 0 (count stops), the pin outputs a low.

13.1.2 Event Counter Mode

In event counter mode, the timer counts pulses from an external device or overflows and underflows of

other timers. Timers A2, A3, and A4 can count two-phase external signals. Table 13.2 lists the Event

Counter Mode Specifications (when not using two-phase pulse signal processing). Figure 13.8 shows

TAiMR Register in Event Counter Mode (when not using two-phase pulse signal processing). Table 13.3

lists the Event Counter Mode Specifications (when using two-phase pulse signal processing with timers

A2, A3, and A4). Figure 13.9 shows Registers TA2MR to TA4MR in Event Counter Mode (when using

two-phase pulse signa processing with timers A2, A3, and A4).

Table 13.2 Event Counter Mode Specifications (when not using two-phase pulse signal processing)

i = 0 to 4

j = i - 1, except j = 4 if i = 0

k = i + 1, except k = 0 if i = 4

1 2 ... 139 140 141 142 143 144 145 146 147 148 149 ... 411 412

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