Renesas M16C/6NK Informações Técnicas descarregar pdf (Página 84)

Rev.2.10 Apr 14, 2006 page 60 of 378

REJ09B0124-0210

M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit

Figure 8.4 CM2 Register

Oscillation Stop Detection Register

(1)

Symbol

Address

After Reset

CM2 000Ch 0X000000b

(2)

Function

b7 b6 b5 b4 b3 b2 b1 b0

Bit Symbol

Bit Name

0 : Oscillation stop, re-oscillation

detection function disabled

1 : Oscillation stop, re-oscillation

detection function enabled

0 : Main clock or PLL clock

1 : On-chip oscillator clock

(On-chip oscillator oscillates)

CM20

CM21

CM22

0 : Main clock stop, re-oscillation

not detected

1 : Main clock stop, re-oscillation

detected

System clock select

bit 2

(2) (5) (6) (7) (8) (11)

CM23

(b5-b4)

(b6)

XIN monitor flag

(10)

0 : Main clock oscillates

1 : Main clock stops

CM27

Operation select bit

(when an

oscillation stop,

re-oscillation is detected)

(2)

0 : Oscillation stop detection reset

1 : Oscillation stop, re-oscillation

detection interrupt

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

Reserved bits Set to 0

NOTES:

1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).

2. Bits CM20, CM21, and CM27 remain unchanged at oscillation stop detection reset.

3. Set the CM20 bit to 0 (disabled) before entering stop mode. Exit stop mode before setting the CM20 bit

back to 1 (enabled).

4. Set the CM20 bit to 0 (disabled) before setting the CM05 bit in the CM0 register to 1 (main clock stops).

5. When the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled), the CM27 bit is

set to 1 (oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock,

the CM21 bit is set to 1 (on-chip oscillator clock) if the main clock stop is detected.

6. If the CM20 bit is set to 1 and the CM23 bit is set to 1 (main clock stops), do not set the CM21 bit to 0.

7. This bit is valid when the CM07 bit in the CM0 register is set to 0.

8. Where the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled), the CM27 bit is

set to 1 (oscillation stop, re-oscillation detection interrupt), and the CM11 bit is set to 1 (PLL clock is selected

as the CPU clock source), the CM21 bit remains unchanged even if a main clock stop is detected. When the

CM22 bit is set to 0 under these conditions, an oscillation stop, re-oscillation detection interrupt request is

generated at main clock stop detection. Set the CM21 bit to 1 (on-chip oscillator clock) in the interrupt routine.

9. This bit is set to 1 when the main clock is detected and the main clock re-oscillation is detected. When this

bit changes state from 0 to 1, an oscillation stop and re-oscillation detection interrupt request is generated.

Use this bit in an interrupt routine to discriminate the interrupt sources between the oscillation stop and

re-oscillation detection interrupt and the watchdog timer interrupt. This bit is set to 0 by writing 0 in a

program. (This bit remains unchanged even if writing 1. Nor is it set to 0 when an oscillation stop and

re-oscillation detection interrupt request is acknowledged.)

If an oscillation stop or a re-oscillation is detected when the CM22 bit = 1, no oscillation stop and re-oscillation

detection interrupt requests are generated.

10. Determine the main clock status by reading the CM23 bit several times in an oscillation stop or re-oscillation

detection interrupt routine.

11. When the CM21 bit is set to 0 (on-chip oscillator stops) and the CM05 bit is set to 1 (main clock stops),

the CM06 bit is fixed to 1 (divide-by-8 mode) and the CM15 bit is fixed to 1 (drive capability high).

Oscillation stop,

re-oscillation detection

enable bit

(2) (3) (4)

Oscillation stop,

re-oscillation detection

flag

(9)

1 2 ... 79 80 81 82 83 84 85 86 87 88 89 ... 411 412

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