Renesas M16C/6NK Informações Técnicas descarregar pdf (Página 91)

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Rev.2.10 Apr 14, 2006 page 67 of 378

REJ09B0124-0210

M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit

Figure 8.11 Procedure to Use PLL Clock as CPU Clock Source

Set bits PLC02 to PLC00 (multiplying factor).

(When PLL clock > 16 MHz)

Set the PM20 bit to 0 (2-wait state).

Set the PLC07 bit to 1 (PLL operation).

Set the CM11 bit to 1 (PLL clock for the CPU clock source).

END

Using the PLL clock as the clock source for the CPU

Set the CM07 bit to 0 (main clock), bits CM17 to CM16

to 00b (main clock undivided), and the CM06 bit to 0

(bits CM16 and CM17 enabled).

(1)

NOTE:

1. PLL operating mode can be entered from high-speed mode.

Wait until the PLL clock becomes stable (tsu(PLL)).

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